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Klafyvel 2018-01-24 17:28:00 +01:00
parent 8dbb559a35
commit 4cd8f015ee
124 changed files with 11544 additions and 14 deletions
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5
README.md Normal file
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Nom + numéro de bin
Les fichiers de simulation sont dans le répertoire SLEA.
Le fichier de projet est Chronometre.qpf.
Le fichier qui doit se trouver en `top hierarchy` est CHRONO.bdf.

522
SLEA/BoutonPoussoir.bdf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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163
SLEA/BoutonPoussoir.vwf Normal file
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@ -0,0 +1,163 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 1000.0;
SIMULATION_TIME = 1000.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 10.0;
GRID_DUTY_CYCLE = 50;
}
SIGNAL("BP")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("BPs")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("H")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("S")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
TRANSITION_LIST("BP")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 130.0;
LEVEL 1 FOR 270.0;
LEVEL 0 FOR 600.0;
}
}
TRANSITION_LIST("BPs")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 150.0;
LEVEL 1 FOR 300.0;
LEVEL 0 FOR 550.0;
}
}
TRANSITION_LIST("H")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 10;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
}
}
}
TRANSITION_LIST("S")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 250.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 650.0;
}
}
DISPLAY_LINE
{
CHANNEL = "H";
EXPAND_STATUS = COLLAPSED;
RADIX = ASCII;
TREE_INDEX = 0;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "BP";
EXPAND_STATUS = COLLAPSED;
RADIX = ASCII;
TREE_INDEX = 1;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "BPs";
EXPAND_STATUS = COLLAPSED;
RADIX = ASCII;
TREE_INDEX = 2;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "S";
EXPAND_STATUS = COLLAPSED;
RADIX = ASCII;
TREE_INDEX = 3;
TREE_LEVEL = 0;
}
TIME_BAR
{
TIME = 0;
MASTER = TRUE;
}
;

328
SLEA/BoutonPoussoir2.bdf Normal file
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@ -0,0 +1,328 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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(text "INPUT" (rect 133 0 161 10)(font "Arial" (font_size 6)))
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57
SLEA/BoutonPoussoir2.bsf Normal file
View file

@ -0,0 +1,57 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 112 112)
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(text "inst" (rect 8 80 25 92)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "BP" (rect 0 0 15 14)(font "Arial" (font_size 8)))
(text "BP" (rect 21 27 36 41)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
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)
)

169
SLEA/BoutonPoussoir2.vwf Normal file
View file

@ -0,0 +1,169 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 1000.0;
SIMULATION_TIME = 1000.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 10.0;
GRID_DUTY_CYCLE = 50;
}
SIGNAL("BP")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("BPs")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("H")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("S")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
TRANSITION_LIST("BP")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 130.0;
LEVEL 1 FOR 270.0;
LEVEL 0 FOR 110.0;
LEVEL 1 FOR 190.0;
LEVEL 0 FOR 300.0;
}
}
TRANSITION_LIST("BPs")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 150.0;
LEVEL 1 FOR 300.0;
LEVEL 0 FOR 100.0;
LEVEL 1 FOR 200.0;
LEVEL 0 FOR 250.0;
}
}
TRANSITION_LIST("H")
{
NODE
{
REPEAT = 1;
NODE
{
REPEAT = 10;
LEVEL 0 FOR 50.0;
LEVEL 1 FOR 50.0;
}
}
}
TRANSITION_LIST("S")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 150.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 300.0;
LEVEL 1 FOR 100.0;
LEVEL 0 FOR 350.0;
}
}
DISPLAY_LINE
{
CHANNEL = "H";
EXPAND_STATUS = COLLAPSED;
RADIX = ASCII;
TREE_INDEX = 0;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "BP";
EXPAND_STATUS = COLLAPSED;
RADIX = ASCII;
TREE_INDEX = 1;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "BPs";
EXPAND_STATUS = COLLAPSED;
RADIX = ASCII;
TREE_INDEX = 2;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "S";
EXPAND_STATUS = COLLAPSED;
RADIX = ASCII;
TREE_INDEX = 3;
TREE_LEVEL = 0;
}
TIME_BAR
{
TIME = 27175;
MASTER = TRUE;
}
;

893
SLEA/CHRONO.bdf Normal file
View file

@ -0,0 +1,893 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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1421
SLEA/CheminDeDonnees.bdf Normal file
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File diff suppressed because it is too large Load diff

162
SLEA/CheminDeDonnees.bsf Normal file
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@ -0,0 +1,162 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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(output)
(text "f1" (rect 0 0 11 14)(font "Arial" (font_size 8)))
(text "f1" (rect 144 107 155 121)(font "Arial" (font_size 8)))
(line (pt 176 112)(pt 160 112)(line_width 1))
)
(port
(pt 176 128)
(output)
(text "g1" (rect 0 0 14 14)(font "Arial" (font_size 8)))
(text "g1" (rect 141 123 155 137)(font "Arial" (font_size 8)))
(line (pt 176 128)(pt 160 128)(line_width 1))
)
(port
(pt 176 144)
(output)
(text "A" (rect 0 0 9 14)(font "Arial" (font_size 8)))
(text "A" (rect 146 139 155 153)(font "Arial" (font_size 8)))
(line (pt 176 144)(pt 160 144)(line_width 1))
)
(port
(pt 176 160)
(output)
(text "B" (rect 0 0 8 14)(font "Arial" (font_size 8)))
(text "B" (rect 147 155 155 169)(font "Arial" (font_size 8)))
(line (pt 176 160)(pt 160 160)(line_width 1))
)
(port
(pt 176 176)
(output)
(text "C" (rect 0 0 8 14)(font "Arial" (font_size 8)))
(text "C" (rect 147 171 155 185)(font "Arial" (font_size 8)))
(line (pt 176 176)(pt 160 176)(line_width 1))
)
(port
(pt 176 192)
(output)
(text "D" (rect 0 0 8 14)(font "Arial" (font_size 8)))
(text "D" (rect 147 187 155 201)(font "Arial" (font_size 8)))
(line (pt 176 192)(pt 160 192)(line_width 1))
)
(port
(pt 176 208)
(output)
(text "E" (rect 0 0 7 14)(font "Arial" (font_size 8)))
(text "E" (rect 148 203 155 217)(font "Arial" (font_size 8)))
(line (pt 176 208)(pt 160 208)(line_width 1))
)
(port
(pt 176 224)
(output)
(text "F" (rect 0 0 7 14)(font "Arial" (font_size 8)))
(text "F" (rect 148 219 155 233)(font "Arial" (font_size 8)))
(line (pt 176 224)(pt 160 224)(line_width 1))
)
(port
(pt 176 240)
(output)
(text "G" (rect 0 0 9 14)(font "Arial" (font_size 8)))
(text "G" (rect 146 235 155 249)(font "Arial" (font_size 8)))
(line (pt 176 240)(pt 160 240)(line_width 1))
)
(port
(pt 176 256)
(output)
(text "pointSeconde" (rect 0 0 77 14)(font "Arial" (font_size 8)))
(text "pointSeconde" (rect 78 251 155 265)(font "Arial" (font_size 8)))
(line (pt 176 256)(pt 160 256)(line_width 1))
)
(port
(pt 176 272)
(output)
(text "pointDixieme" (rect 0 0 70 14)(font "Arial" (font_size 8)))
(text "pointDixieme" (rect 85 267 155 281)(font "Arial" (font_size 8)))
(line (pt 176 272)(pt 160 272)(line_width 1))
)
(drawing
(rectangle (rect 16 16 160 304)(line_width 1))
)
)

1110
SLEA/CheminDeDonnées.bdf Normal file
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File diff suppressed because it is too large Load diff

125
SLEA/Chronometre.asm.rpt Normal file
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@ -0,0 +1,125 @@
Assembler report for Chronometre
Wed Jan 24 17:22:07 2018
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Assembler Summary
3. Assembler Settings
4. Assembler Generated Files
5. Assembler Device Options: E:/SLEA/Chronometre.sof
6. Assembler Device Options: E:/SLEA/Chronometre.pof
7. Assembler Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------+
; Assembler Summary ;
+-----------------------+---------------------------------------+
; Assembler Status ; Successful - Wed Jan 24 17:22:07 2018 ;
; Revision Name ; Chronometre ;
; Top-level Entity Name ; CHRONO ;
; Family ; FLEX10K ;
; Device ; EPF10K70RC240-4 ;
+-----------------------+---------------------------------------+
+--------------------------------------------------------------------------------------------------------+
; Assembler Settings ;
+-----------------------------------------------------------------------------+----------+---------------+
; Option ; Setting ; Default Value ;
+-----------------------------------------------------------------------------+----------+---------------+
; Use smart compilation ; On ; Off ;
; Compression mode ; Off ; Off ;
; Clock source for configuration device ; Internal ; Internal ;
; Clock frequency of the configuration device ; 10 MHZ ; 10 MHz ;
; Divide clock frequency by ; 1 ; 1 ;
; Low-voltage mode ; On ; On ;
; Use configuration device ; On ; On ;
; Configuration device ; Auto ; Auto ;
; Configuration device auto user code ; Off ; Off ;
; Generate Tabular Text File (.ttf) For Target Device ; Off ; Off ;
; Generate Raw Binary File (.rbf) For Target Device ; Off ; Off ;
; Generate Hexadecimal (Intel-Format) Output File (.hexout) for Target Device ; Off ; Off ;
; Hexadecimal Output File start address ; 0 ; 0 ;
; Hexadecimal Output File count direction ; Up ; Up ;
; Release clears before tri-states ; Off ; Off ;
; Auto-restart configuration after error ; On ; On ;
; Generate Serial Vector Format File (.svf) for Target Device ; Off ; Off ;
; Generate a JEDEC STAPL Format File (.jam) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; Off ; Off ;
; Generate a compressed Jam STAPL Byte Code 2.0 File (.jbc) for Target Device ; On ; On ;
+-----------------------------------------------------------------------------+----------+---------------+
+---------------------------+
; Assembler Generated Files ;
+---------------------------+
; File Name ;
+---------------------------+
; E:/SLEA/Chronometre.sof ;
; E:/SLEA/Chronometre.pof ;
+---------------------------+
+---------------------------------------------------+
; Assembler Device Options: E:/SLEA/Chronometre.sof ;
+----------------+----------------------------------+
; Option ; Setting ;
+----------------+----------------------------------+
; Device ; EPF10K70RC240-4 ;
; JTAG usercode ; 0x0000007F ;
; Checksum ; 0x0001F97E ;
+----------------+----------------------------------+
+---------------------------------------------------+
; Assembler Device Options: E:/SLEA/Chronometre.pof ;
+--------------------+------------------------------+
; Option ; Setting ;
+--------------------+------------------------------+
; Device ; EPC2 ;
; JTAG usercode ; 0x00000000 ;
; Checksum ; 0x018BE48A ;
; Compression Ratio ; 1 ;
+--------------------+------------------------------+
+--------------------+
; Assembler Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Assembler
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Info: Processing started: Wed Jan 24 17:22:06 2018
Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off Chronometre -c Chronometre
Info: Assembler is generating device programming files
Info: Quartus II Assembler was successful. 0 errors, 0 warnings
Info: Peak virtual memory: 176 megabytes
Info: Processing ended: Wed Jan 24 17:22:08 2018
Info: Elapsed time: 00:00:02
Info: Total CPU time (on all processors): 00:00:01

13
SLEA/Chronometre.cdf Normal file
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@ -0,0 +1,13 @@
/* Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition */
JedecChain;
FileRevision(JESD32A);
DefaultMfr(6E);
P ActionCode(Cfg)
Device PartName(EPF10K70R240) Path("U:/SLEA/") File("Chronometre.sof") MfrSpec(OpMask(1));
ChainEnd;
AlteraBegin;
ChainType(JTAG);
AlteraEnd;

1
SLEA/Chronometre.done Normal file
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@ -0,0 +1 @@
Wed Jan 24 17:22:11 2018

12
SLEA/Chronometre.dpf Normal file
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@ -0,0 +1,12 @@
<?xml version="1.0" encoding="UTF-8"?>
<pin_planner>
<pin_info>
</pin_info>
<buses>
</buses>
<group_file_association>
</group_file_association>
<pin_planner_file_specifies>
</pin_planner_file_specifies>
</pin_planner>

788
SLEA/Chronometre.fit.rpt Normal file
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@ -0,0 +1,788 @@
Fitter report for Chronometre
Wed Jan 24 17:22:04 2018
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Fitter Summary
3. Fitter Settings
4. Parallel Compilation
5. Fitter Device Options
6. Input Pins
7. Output Pins
8. All Package Pins
9. Control Signals
10. Global & Other Fast Signals
11. Carry Chains
12. Non-Global High Fan-Out Signals
13. Peripheral Signals
14. LAB
15. Local Routing Interconnect
16. LAB External Interconnect
17. Row Interconnect
18. LAB Column Interconnect
19. LAB Column Interconnect
20. Fitter Resource Usage Summary
21. Fitter Resource Utilization by Entity
22. Delay Chain Summary
23. Pin-Out File
24. Fitter Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+----------------------------------------------------------------------+
; Fitter Summary ;
+-----------------------+----------------------------------------------+
; Fitter Status ; Successful - Wed Jan 24 17:22:04 2018 ;
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
; Revision Name ; Chronometre ;
; Top-level Entity Name ; CHRONO ;
; Family ; FLEX10K ;
; Device ; EPF10K70RC240-4 ;
; Timing Models ; Final ;
; Total logic elements ; 70 / 3,744 ( 2 % ) ;
; Total pins ; 22 / 189 ( 12 % ) ;
; Total memory bits ; 0 / 18,432 ( 0 % ) ;
+-----------------------+----------------------------------------------+
+------------------------------------------------------------------------------------------------------+
; Fitter Settings ;
+------------------------------------------------------------+--------------------+--------------------+
; Option ; Setting ; Default Value ;
+------------------------------------------------------------+--------------------+--------------------+
; Device ; EPF10K70RC240-4 ; ;
; Use smart compilation ; On ; Off ;
; Use TimeQuest Timing Analyzer ; Off ; Off ;
; Router Timing Optimization Level ; Normal ; Normal ;
; Placement Effort Multiplier ; 1.0 ; 1.0 ;
; Router Effort Multiplier ; 1.0 ; 1.0 ;
; Optimize Timing ; Normal compilation ; Normal compilation ;
; Optimize Timing for ECOs ; Off ; Off ;
; Regenerate full fit report during ECO compiles ; Off ; Off ;
; Optimize IOC Register Placement for Timing ; On ; On ;
; Limit to One Fitting Attempt ; Off ; Off ;
; Final Placement Optimizations ; Automatically ; Automatically ;
; Fitter Aggressive Routability Optimizations ; Automatically ; Automatically ;
; Fitter Initial Placement Seed ; 1 ; 1 ;
; Slow Slew Rate ; Off ; Off ;
; Auto Global Memory Control Signals ; Off ; Off ;
; Logic Cell Insertion - Individual Logic Cells ; On ; On ;
; Logic Cell Insertion - I/Os Fed By Carry or Cascade Chains ; On ; On ;
; Fitter Effort ; Auto Fit ; Auto Fit ;
; Auto Global Clock ; On ; On ;
; Auto Global Output Enable ; On ; On ;
; Auto Global Register Control Signals ; On ; On ;
; Force Fitter to Avoid Periphery Placement Warnings ; Off ; Off ;
+------------------------------------------------------------+--------------------+--------------------+
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation ;
+----------------------------+--------+
; Processors ; Number ;
+----------------------------+--------+
; Number detected on machine ; 2 ;
; Maximum allowed ; 1 ;
+----------------------------+--------+
+-------------------------------------------------------------------------+
; Fitter Device Options ;
+----------------------------------------------+--------------------------+
; Option ; Setting ;
+----------------------------------------------+--------------------------+
; Enable user-supplied start-up clock (CLKUSR) ; Off ;
; Enable device-wide reset (DEV_CLRn) ; Off ;
; Enable device-wide output enable (DEV_OE) ; Off ;
; Enable INIT_DONE output ; Off ;
; Configuration scheme ; Passive Serial ;
; nWS, nRS, nCS, CS ; Unreserved ;
; RDYnBUSY ; Unreserved ;
; Data[7..1] ; Unreserved ;
; Reserve all unused pins ; As output driving ground ;
; Base pin-out file on sameframe device ; Off ;
+----------------------------------------------+--------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------+
; Input Pins ;
+------+-------+-----+------+---------+--------+--------------+-------------------------+---------------+---------------+--------------+
; Name ; Pin # ; Row ; Col. ; Fan-Out ; Global ; I/O Register ; Use Local Routing Input ; Power Up High ; Single-Pin CE ; I/O Standard ;
+------+-------+-----+------+---------+--------+--------------+-------------------------+---------------+---------------+--------------+
; BP1 ; 28 ; D ; -- ; 1 ; no ; no ; no ; no ; no ; TTL ;
; BP2 ; 29 ; D ; -- ; 1 ; no ; no ; no ; no ; no ; TTL ;
; H ; 91 ; -- ; -- ; 3 ; yes ; no ; no ; no ; no ; TTL ;
+------+-------+-----+------+---------+--------+--------------+-------------------------+---------------+---------------+--------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Output Pins ;
+--------------+-------+-----+------+--------------+--------------------------+---------------+----------------+---------------+---------------+------------+---------------+--------------+
; Name ; Pin # ; Row ; Col. ; I/O Register ; Use Local Routing Output ; Power Up High ; Slow Slew Rate ; Single-Pin OE ; Single-Pin CE ; Open Drain ; TRI Primitive ; I/O Standard ;
+--------------+-------+-----+------+--------------+--------------------------+---------------+----------------+---------------+---------------+------------+---------------+--------------+
; A ; 6 ; A ; -- ; no ; no ; no ; no ; no ; no ; no ; no ; TTL ;
; Count ; 48 ; H ; -- ; no ; no ; no ; no ; no ; no ; no ; no ; TTL ;
; Reset ; 53 ; I ; -- ; no ; no ; no ; no ; no ; no ; no ; no ; TTL ;
; B ; 7 ; A ; -- ; no ; no ; no ; no ; no ; no ; no ; no ; TTL ;
; C ; 8 ; A ; -- ; no ; no ; no ; no ; no ; no ; no ; no ; TTL ;
; D ; 9 ; A ; -- ; no ; no ; no ; no ; no ; no ; no ; no ; TTL ;
; E ; 11 ; A ; -- ; no ; no ; no ; no ; no ; no ; no ; no ; TTL ;
; F ; 12 ; B ; -- ; no ; no ; no ; no ; no ; no ; no ; no ; TTL ;
; G ; 13 ; B ; -- ; no ; no ; no ; no ; no ; no ; no ; no ; TTL ;
; a1 ; 17 ; B ; -- ; no ; no ; no ; no ; no ; no ; no ; no ; TTL ;
; b1 ; 18 ; B ; -- ; no ; no ; no ; no ; no ; no ; no ; no ; TTL ;
; c1 ; 19 ; C ; -- ; no ; no ; no ; no ; no ; no ; no ; no ; TTL ;
; e1 ; 21 ; C ; -- ; no ; no ; no ; no ; no ; no ; no ; no ; TTL ;
; f1 ; 23 ; C ; -- ; no ; no ; no ; no ; no ; no ; no ; no ; TTL ;
; g1 ; 24 ; C ; -- ; no ; no ; no ; no ; no ; no ; no ; no ; TTL ;
; d1 ; 20 ; C ; -- ; no ; no ; no ; no ; no ; no ; no ; no ; TTL ;
; BP1out ; 45 ; G ; -- ; no ; no ; no ; no ; no ; no ; no ; no ; TTL ;
; pointSeconde ; 25 ; D ; -- ; no ; no ; no ; no ; no ; no ; no ; no ; TTL ;
; pointDixieme ; 14 ; B ; -- ; no ; no ; no ; no ; no ; no ; no ; no ; TTL ;
+--------------+-------+-----+------+--------------+--------------------------+---------------+----------------+---------------+---------------+------------+---------------+--------------+
+-------------------------------------+
; All Package Pins ;
+-------+--------------+--------------+
; Pin # ; Usage ; I/O Standard ;
+-------+--------------+--------------+
; 1 ; #TCK ; ;
; 2 ; ^CONF_DONE ; ;
; 3 ; ^nCEO ; ;
; 4 ; #TDO ; ;
; 5 ; VCC_INT ; ;
; 6 ; A ; TTL ;
; 7 ; B ; TTL ;
; 8 ; C ; TTL ;
; 9 ; D ; TTL ;
; 10 ; GND_INT ; ;
; 11 ; E ; TTL ;
; 12 ; F ; TTL ;
; 13 ; G ; TTL ;
; 14 ; pointDixieme ; TTL ;
; 15 ; GND* ; ;
; 16 ; VCC_INT ; ;
; 17 ; a1 ; TTL ;
; 18 ; b1 ; TTL ;
; 19 ; c1 ; TTL ;
; 20 ; d1 ; TTL ;
; 21 ; e1 ; TTL ;
; 22 ; GND_INT ; ;
; 23 ; f1 ; TTL ;
; 24 ; g1 ; TTL ;
; 25 ; pointSeconde ; TTL ;
; 26 ; GND* ; ;
; 27 ; VCC_INT ; ;
; 28 ; BP1 ; TTL ;
; 29 ; BP2 ; TTL ;
; 30 ; GND* ; ;
; 31 ; GND* ; ;
; 32 ; GND_INT ; ;
; 33 ; GND* ; ;
; 34 ; GND* ; ;
; 35 ; GND* ; ;
; 36 ; GND* ; ;
; 37 ; VCC_INT ; ;
; 38 ; GND* ; ;
; 39 ; GND* ; ;
; 40 ; GND* ; ;
; 41 ; GND* ; ;
; 42 ; GND_INT ; ;
; 43 ; GND* ; ;
; 44 ; GND* ; ;
; 45 ; BP1out ; TTL ;
; 46 ; GND* ; ;
; 47 ; VCC_INT ; ;
; 48 ; Count ; TTL ;
; 49 ; GND* ; ;
; 50 ; GND* ; ;
; 51 ; GND* ; ;
; 52 ; GND_INT ; ;
; 53 ; Reset ; TTL ;
; 54 ; GND* ; ;
; 55 ; GND* ; ;
; 56 ; GND* ; ;
; 57 ; VCC_INT ; ;
; 58 ; #TMS ; ;
; 59 ; #TRST ; ;
; 60 ; ^nSTATUS ; ;
; 61 ; GND* ; ;
; 62 ; GND* ; ;
; 63 ; GND* ; ;
; 64 ; GND* ; ;
; 65 ; GND* ; ;
; 66 ; GND* ; ;
; 67 ; GND* ; ;
; 68 ; GND* ; ;
; 69 ; GND_INT ; ;
; 70 ; GND* ; ;
; 71 ; GND* ; ;
; 72 ; GND* ; ;
; 73 ; GND* ; ;
; 74 ; GND* ; ;
; 75 ; GND* ; ;
; 76 ; GND* ; ;
; 77 ; VCC_INT ; ;
; 78 ; GND* ; ;
; 79 ; GND* ; ;
; 80 ; GND* ; ;
; 81 ; GND* ; ;
; 82 ; GND* ; ;
; 83 ; GND* ; ;
; 84 ; GND* ; ;
; 85 ; GND_INT ; ;
; 86 ; GND* ; ;
; 87 ; GND* ; ;
; 88 ; GND* ; ;
; 89 ; VCC_INT ; ;
; 90 ; GND+ ; ;
; 91 ; H ; TTL ;
; 92 ; GND+ ; ;
; 93 ; GND_INT ; ;
; 94 ; GND* ; ;
; 95 ; GND* ; ;
; 96 ; VCC_INT ; ;
; 97 ; GND* ; ;
; 98 ; GND* ; ;
; 99 ; GND* ; ;
; 100 ; GND* ; ;
; 101 ; GND* ; ;
; 102 ; GND* ; ;
; 103 ; GND* ; ;
; 104 ; GND_INT ; ;
; 105 ; GND* ; ;
; 106 ; GND* ; ;
; 107 ; GND* ; ;
; 108 ; GND* ; ;
; 109 ; GND* ; ;
; 110 ; GND* ; ;
; 111 ; GND* ; ;
; 112 ; VCC_INT ; ;
; 113 ; GND* ; ;
; 114 ; GND* ; ;
; 115 ; GND* ; ;
; 116 ; GND* ; ;
; 117 ; GND* ; ;
; 118 ; GND* ; ;
; 119 ; GND* ; ;
; 120 ; GND* ; ;
; 121 ; ^nCONFIG ; ;
; 122 ; VCC_INT ; ;
; 123 ; ^MSEL1 ; ;
; 124 ; ^MSEL0 ; ;
; 125 ; GND_INT ; ;
; 126 ; GND* ; ;
; 127 ; GND* ; ;
; 128 ; GND* ; ;
; 129 ; GND* ; ;
; 130 ; VCC_INT ; ;
; 131 ; GND* ; ;
; 132 ; GND* ; ;
; 133 ; GND* ; ;
; 134 ; GND* ; ;
; 135 ; GND_INT ; ;
; 136 ; GND* ; ;
; 137 ; GND* ; ;
; 138 ; GND* ; ;
; 139 ; GND* ; ;
; 140 ; VCC_INT ; ;
; 141 ; GND* ; ;
; 142 ; GND* ; ;
; 143 ; GND* ; ;
; 144 ; GND* ; ;
; 145 ; GND_INT ; ;
; 146 ; GND* ; ;
; 147 ; GND* ; ;
; 148 ; GND* ; ;
; 149 ; GND* ; ;
; 150 ; VCC_INT ; ;
; 151 ; GND* ; ;
; 152 ; GND* ; ;
; 153 ; GND* ; ;
; 154 ; GND* ; ;
; 155 ; GND_INT ; ;
; 156 ; GND* ; ;
; 157 ; GND* ; ;
; 158 ; GND* ; ;
; 159 ; GND* ; ;
; 160 ; VCC_INT ; ;
; 161 ; GND* ; ;
; 162 ; GND* ; ;
; 163 ; GND* ; ;
; 164 ; GND* ; ;
; 165 ; GND_INT ; ;
; 166 ; GND* ; ;
; 167 ; GND* ; ;
; 168 ; GND* ; ;
; 169 ; GND* ; ;
; 170 ; VCC_INT ; ;
; 171 ; GND* ; ;
; 172 ; GND* ; ;
; 173 ; GND* ; ;
; 174 ; GND* ; ;
; 175 ; GND* ; ;
; 176 ; GND_INT ; ;
; 177 ; #TDI ; ;
; 178 ; ^nCE ; ;
; 179 ; ^DCLK ; ;
; 180 ; ^DATA0 ; ;
; 181 ; GND* ; ;
; 182 ; GND* ; ;
; 183 ; GND* ; ;
; 184 ; GND* ; ;
; 185 ; GND* ; ;
; 186 ; GND* ; ;
; 187 ; GND* ; ;
; 188 ; GND* ; ;
; 189 ; VCC_INT ; ;
; 190 ; GND* ; ;
; 191 ; GND* ; ;
; 192 ; GND* ; ;
; 193 ; GND* ; ;
; 194 ; GND* ; ;
; 195 ; GND* ; ;
; 196 ; GND* ; ;
; 197 ; GND_INT ; ;
; 198 ; GND* ; ;
; 199 ; GND* ; ;
; 200 ; GND* ; ;
; 201 ; GND* ; ;
; 202 ; GND* ; ;
; 203 ; GND* ; ;
; 204 ; GND* ; ;
; 205 ; VCC_INT ; ;
; 206 ; GND* ; ;
; 207 ; GND* ; ;
; 208 ; GND* ; ;
; 209 ; GND* ; ;
; 210 ; GND+ ; ;
; 211 ; GND+ ; ;
; 212 ; GND+ ; ;
; 213 ; GND* ; ;
; 214 ; GND* ; ;
; 215 ; GND* ; ;
; 216 ; GND_INT ; ;
; 217 ; GND* ; ;
; 218 ; GND* ; ;
; 219 ; GND* ; ;
; 220 ; GND* ; ;
; 221 ; GND* ; ;
; 222 ; GND* ; ;
; 223 ; GND* ; ;
; 224 ; VCC_INT ; ;
; 225 ; GND* ; ;
; 226 ; GND* ; ;
; 227 ; GND* ; ;
; 228 ; GND* ; ;
; 229 ; GND* ; ;
; 230 ; GND* ; ;
; 231 ; GND* ; ;
; 232 ; GND_INT ; ;
; 233 ; GND* ; ;
; 234 ; GND* ; ;
; 235 ; GND* ; ;
; 236 ; GND* ; ;
; 237 ; GND* ; ;
; 238 ; GND* ; ;
; 239 ; GND* ; ;
; 240 ; GND* ; ;
+-------+--------------+--------------+
+---------------------------------------------------------------------------------------------------------------------+
; Control Signals ;
+-------------------------------------------------------------------+---------+---------+--------------+--------------+
; Name ; Pin # ; Fan-Out ; Usage ; Global Usage ;
+-------------------------------------------------------------------+---------+---------+--------------+--------------+
; H ; 91 ; 3 ; Clock ; Pin ;
; DiviseurDeFrequence:inst1|7456:inst7|5 ; LC1_H41 ; 18 ; Clock ; Non-global ;
; DiviseurDeFrequence:inst1|7456:inst7|3 ; LC3_H41 ; 3 ; Clock enable ; Non-global ;
; DiviseurDeFrequence:inst1|inst10 ; LC1_H27 ; 18 ; Clock ; Internal ;
; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|302~5_wirecell ; LC3_H27 ; 7 ; Sync. clear ; Non-global ;
+-------------------------------------------------------------------+---------+---------+--------------+--------------+
+---------------------------------------------------------------+
; Global & Other Fast Signals ;
+----------------------------------+---------+---------+--------+
; Name ; Pin # ; Fan-Out ; Global ;
+----------------------------------+---------+---------+--------+
; H ; 91 ; 3 ; yes ;
; DiviseurDeFrequence:inst1|inst10 ; LC1_H27 ; 18 ; yes ;
+----------------------------------+---------+---------+--------+
+---------------------------------------------+
; Carry Chains ;
+--------------------+------------------------+
; Carry Chain Length ; Number of Carry Chains ;
+--------------------+------------------------+
; 0 ; 0 ;
; 1 ; 0 ;
; 2 ; 0 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 0 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 0 ;
; 17 ; 1 ;
+--------------------+------------------------+
+-----------------------------------------------------------------------------+
; Non-Global High Fan-Out Signals ;
+-------------------------------------------------------------------+---------+
; Name ; Fan-Out ;
+-------------------------------------------------------------------+---------+
; DiviseurDeFrequence:inst1|7456:inst7|5~0 ; 18 ;
; CheminDeDonnees:inst|74168:inst2|3~0 ; 12 ;
; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|302~8 ; 11 ;
; CheminDeDonnees:inst|74168:inst1|49~0 ; 11 ;
; BoutonPoussoir2:inst15|inst3~0 ; 11 ;
; CheminDeDonnees:inst|74168:inst1|3~0 ; 11 ;
; sequenceur2:inst17|inst3~0 ; 10 ;
; CheminDeDonnees:inst|74168:inst1|15~0 ; 10 ;
; CheminDeDonnees:inst|74168:inst2|15~0 ; 10 ;
; CheminDeDonnees:inst|74168:inst1|29~0 ; 9 ;
; BoutonPoussoir2:inst15|inst~1 ; 9 ;
; CheminDeDonnees:inst|74168:inst2|29~0 ; 9 ;
; CheminDeDonnees:inst|74168:inst8|3~0 ; 8 ;
; BoutonPoussoir2:inst15|inst5~1 ; 8 ;
; CheminDeDonnees:inst|74168:inst2|49~0 ; 8 ;
; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|302~5_wirecell ; 7 ;
; CheminDeDonnees:inst|74168:inst1|77~1 ; 5 ;
; CheminDeDonnees:inst|74168:inst8|49~0 ; 5 ;
; CheminDeDonnees:inst|74168:inst8|15~0 ; 3 ;
; CheminDeDonnees:inst|74168:inst1|77~2 ; 3 ;
; DiviseurDeFrequence:inst1|7456:inst7|3~0 ; 3 ;
; CheminDeDonnees:inst|74168:inst8|29~0 ; 2 ;
; CheminDeDonnees:inst|74168:inst8|50~4 ; 2 ;
; CheminDeDonnees:inst|74168:inst8|77~0 ; 2 ;
; CheminDeDonnees:inst|74168:inst2|50~4 ; 2 ;
; CheminDeDonnees:inst|74168:inst1|50~4 ; 2 ;
; DiviseurDeFrequence:inst1|7456:inst7|4~1 ; 2 ;
; BoutonPoussoir2:inst16|inst~1 ; 2 ;
; BP2 ; 1 ;
; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|248 ; 1 ;
; CheminDeDonnees:inst|7446:inst4|99~1 ; 1 ;
; CheminDeDonnees:inst|74168:inst2|27~2 ; 1 ;
; CheminDeDonnees:inst|74168:inst2|11~2 ; 1 ;
; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|302 ; 1 ;
; CheminDeDonnees:inst|7446:inst4|96~1 ; 1 ;
; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|247 ; 1 ;
; CheminDeDonnees:inst|7446:inst7|102~0 ; 1 ;
; CheminDeDonnees:inst|7446:inst4|98~0 ; 1 ;
; CheminDeDonnees:inst|7446:inst7|101~1 ; 1 ;
; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|247 ; 1 ;
; CheminDeDonnees:inst|7446:inst7|100~0 ; 1 ;
; CheminDeDonnees:inst|74168:inst1|27~2 ; 1 ;
; CheminDeDonnees:inst|7446:inst7|99~1 ; 1 ;
; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|245 ; 1 ;
; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|248 ; 1 ;
; CheminDeDonnees:inst|7446:inst7|98~0 ; 1 ;
; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|249 ; 1 ;
; BoutonPoussoir2:inst15|inst3~1 ; 1 ;
; CheminDeDonnees:inst|74168:inst1|11~2 ; 1 ;
; CheminDeDonnees:inst|7446:inst4|102~0 ; 1 ;
+-------------------------------------------------------------------+---------+
+-------------------------------------------------------------------------------------------------------------+
; Peripheral Signals ;
+----------------------------------+---------+-------+-----------------+---------------------------+----------+
; Peripheral Signal ; Source ; Usage ; Dedicated Clock ; Peripheral Control Signal ; Polarity ;
+----------------------------------+---------+-------+-----------------+---------------------------+----------+
; DiviseurDeFrequence:inst1|inst10 ; LC1_H27 ; Clock ; no ; yes ; +ve ;
+----------------------------------+---------+-------+-----------------+---------------------------+----------+
+-------------------------------------------+
; LAB ;
+--------------------------+----------------+
; Number of Logic Elements ; Number of LABs ;
+--------------------------+----------------+
; 0 ; 453 ;
; 1 ; 3 ;
; 2 ; 1 ;
; 3 ; 2 ;
; 4 ; 0 ;
; 5 ; 3 ;
; 6 ; 1 ;
; 7 ; 2 ;
; 8 ; 3 ;
+--------------------------+----------------+
+----------------------------------------------+
; Local Routing Interconnect ;
+-----------------------------+----------------+
; Local Routing Interconnects ; Number of LABs ;
+-----------------------------+----------------+
; 0 ; 457 ;
; 1 ; 3 ;
; 2 ; 3 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 2 ;
; 6 ; 1 ;
; 7 ; 1 ;
+-----------------------------+----------------+
+---------------------------------------------+
; LAB External Interconnect ;
+----------------------------+----------------+
; LAB External Interconnects ; Number of LABs ;
+----------------------------+----------------+
; 0 ; 454 ;
; 1 ; 2 ;
; 2 ; 3 ;
; 3 ; 1 ;
; 4 ; 3 ;
; 5 ; 1 ;
; 6 ; 2 ;
; 7 ; 1 ;
; 8 ; 1 ;
+----------------------------+----------------+
+------------------------------------------------------------------------------------------+
; Row Interconnect ;
+-------+---------------------+-----------------------------+------------------------------+
; Row ; Interconnect Used ; Left Half Interconnect Used ; Right Half Interconnect Used ;
+-------+---------------------+-----------------------------+------------------------------+
; A ; 0 / 208 ( 0 % ) ; 0 / 104 ( 0 % ) ; 5 / 104 ( 5 % ) ;
; B ; 0 / 208 ( 0 % ) ; 0 / 104 ( 0 % ) ; 4 / 104 ( 4 % ) ;
; C ; 1 / 208 ( < 1 % ) ; 0 / 104 ( 0 % ) ; 5 / 104 ( 5 % ) ;
; D ; 2 / 208 ( < 1 % ) ; 0 / 104 ( 0 % ) ; 0 / 104 ( 0 % ) ;
; E ; 0 / 208 ( 0 % ) ; 0 / 104 ( 0 % ) ; 0 / 104 ( 0 % ) ;
; F ; 0 / 208 ( 0 % ) ; 0 / 104 ( 0 % ) ; 0 / 104 ( 0 % ) ;
; G ; 0 / 208 ( 0 % ) ; 0 / 104 ( 0 % ) ; 1 / 104 ( < 1 % ) ;
; H ; 1 / 208 ( < 1 % ) ; 0 / 104 ( 0 % ) ; 25 / 104 ( 24 % ) ;
; I ; 0 / 208 ( 0 % ) ; 0 / 104 ( 0 % ) ; 1 / 104 ( < 1 % ) ;
; Total ; 4 / 1872 ( < 1 % ) ; 0 / 936 ( 0 % ) ; 41 / 936 ( 4 % ) ;
+-------+---------------------+-----------------------------+------------------------------+
+----------------------------+
; LAB Column Interconnect ;
+-------+--------------------+
; Col. ; Interconnect Used ;
+-------+--------------------+
; 1 ; 0 / 24 ( 0 % ) ;
; 2 ; 0 / 24 ( 0 % ) ;
; 3 ; 0 / 24 ( 0 % ) ;
; 4 ; 0 / 24 ( 0 % ) ;
; 5 ; 0 / 24 ( 0 % ) ;
; 6 ; 0 / 24 ( 0 % ) ;
; 7 ; 0 / 24 ( 0 % ) ;
; 8 ; 0 / 24 ( 0 % ) ;
; 9 ; 0 / 24 ( 0 % ) ;
; 10 ; 0 / 24 ( 0 % ) ;
; 11 ; 0 / 24 ( 0 % ) ;
; 12 ; 0 / 24 ( 0 % ) ;
; 13 ; 0 / 24 ( 0 % ) ;
; 14 ; 0 / 24 ( 0 % ) ;
; 15 ; 0 / 24 ( 0 % ) ;
; 16 ; 0 / 24 ( 0 % ) ;
; 17 ; 0 / 24 ( 0 % ) ;
; 18 ; 0 / 24 ( 0 % ) ;
; 19 ; 0 / 24 ( 0 % ) ;
; 20 ; 0 / 24 ( 0 % ) ;
; 21 ; 0 / 24 ( 0 % ) ;
; 22 ; 0 / 24 ( 0 % ) ;
; 23 ; 0 / 24 ( 0 % ) ;
; 24 ; 0 / 24 ( 0 % ) ;
; 25 ; 0 / 24 ( 0 % ) ;
; 26 ; 0 / 24 ( 0 % ) ;
; 27 ; 0 / 24 ( 0 % ) ;
; 28 ; 1 / 24 ( 4 % ) ;
; 29 ; 0 / 24 ( 0 % ) ;
; 30 ; 1 / 24 ( 4 % ) ;
; 31 ; 0 / 24 ( 0 % ) ;
; 32 ; 0 / 24 ( 0 % ) ;
; 33 ; 0 / 24 ( 0 % ) ;
; 34 ; 0 / 24 ( 0 % ) ;
; 35 ; 6 / 24 ( 25 % ) ;
; 36 ; 1 / 24 ( 4 % ) ;
; 37 ; 0 / 24 ( 0 % ) ;
; 38 ; 0 / 24 ( 0 % ) ;
; 39 ; 1 / 24 ( 4 % ) ;
; 40 ; 0 / 24 ( 0 % ) ;
; 41 ; 0 / 24 ( 0 % ) ;
; 42 ; 5 / 24 ( 21 % ) ;
; 43 ; 1 / 24 ( 4 % ) ;
; 44 ; 0 / 24 ( 0 % ) ;
; 45 ; 0 / 24 ( 0 % ) ;
; 46 ; 0 / 24 ( 0 % ) ;
; 47 ; 0 / 24 ( 0 % ) ;
; 48 ; 1 / 24 ( 4 % ) ;
; 49 ; 1 / 24 ( 4 % ) ;
; 50 ; 0 / 24 ( 0 % ) ;
; 51 ; 1 / 24 ( 4 % ) ;
; 52 ; 0 / 24 ( 0 % ) ;
; Total ; 19 / 1248 ( 2 % ) ;
+-------+--------------------+
+---------------------------+
; LAB Column Interconnect ;
+-------+-------------------+
; Col. ; Interconnect Used ;
+-------+-------------------+
; 1 ; 0 / 24 ( 0 % ) ;
; Total ; 0 / 24 ( 0 % ) ;
+-------+-------------------+
+----------------------------------------------------------------------------+
; Fitter Resource Usage Summary ;
+-----------------------------------+----------------------------------------+
; Resource ; Usage ;
+-----------------------------------+----------------------------------------+
; Total logic elements ; 70 / 3,744 ( 2 % ) ;
; Registers ; 37 / 3,744 ( < 1 % ) ;
; Logic elements in carry chains ; 17 ;
; User inserted logic elements ; 0 ;
; I/O pins ; 22 / 189 ( 12 % ) ;
; -- Clock pins ; 2 / 2 ( 100 % ) ;
; -- Dedicated input pins ; 2 / 4 ( 50 % ) ;
; Global signals ; 2 ;
; EABs ; 0 / 9 ( 0 % ) ;
; Total memory bits ; 0 / 18,432 ( 0 % ) ;
; Total RAM block bits ; 0 / 18,432 ( 0 % ) ;
; Maximum fan-out node ; DiviseurDeFrequence:inst1|inst10 ;
; Maximum fan-out ; 18 ;
; Highest non-global fan-out signal ; DiviseurDeFrequence:inst1|7456:inst7|5 ;
; Highest non-global fan-out ; 18 ;
; Total fan-out ; 259 ;
; Average fan-out ; 2.82 ;
+-----------------------------------+----------------------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Fitter Resource Utilization by Entity ;
+--------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+--------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------+--------------+
; |CHRONO ; 70 (0) ; 37 ; 0 ; 22 ; 33 (0) ; 2 (0) ; 35 (0) ; 17 (0) ; 0 (0) ; |CHRONO ; work ;
; |BoutonPoussoir2:inst15| ; 4 (4) ; 2 ; 0 ; 0 ; 2 (2) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |CHRONO|BoutonPoussoir2:inst15 ; work ;
; |BoutonPoussoir2:inst16| ; 2 (2) ; 2 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |CHRONO|BoutonPoussoir2:inst16 ; work ;
; |CheminDeDonnees:inst| ; 41 (0) ; 12 ; 0 ; 0 ; 29 (0) ; 0 (0) ; 12 (0) ; 0 (0) ; 0 (0) ; |CHRONO|CheminDeDonnees:inst ; work ;
; |74168:inst1| ; 10 (10) ; 4 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |CHRONO|CheminDeDonnees:inst|74168:inst1 ; work ;
; |74168:inst2| ; 8 (8) ; 4 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |CHRONO|CheminDeDonnees:inst|74168:inst2 ; work ;
; |74168:inst8| ; 9 (9) ; 4 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |CHRONO|CheminDeDonnees:inst|74168:inst8 ; work ;
; |7446:inst4| ; 7 (7) ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |CHRONO|CheminDeDonnees:inst|7446:inst4 ; work ;
; |7446:inst7| ; 7 (7) ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |CHRONO|CheminDeDonnees:inst|7446:inst7 ; work ;
; |DiviseurDeFrequence:inst1| ; 22 (1) ; 20 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 20 (1) ; 17 (0) ; 0 (0) ; |CHRONO|DiviseurDeFrequence:inst1 ; work ;
; |7456:inst7| ; 3 (3) ; 3 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 (0) ; |CHRONO|DiviseurDeFrequence:inst1|7456:inst7 ; work ;
; |8count:inst4| ; 10 (0) ; 8 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 8 (0) ; 9 (0) ; 0 (0) ; |CHRONO|DiviseurDeFrequence:inst1|8count:inst4 ; work ;
; |f8count:sub| ; 10 (10) ; 8 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 8 (8) ; 9 (9) ; 0 (0) ; |CHRONO|DiviseurDeFrequence:inst1|8count:inst4|f8count:sub ; work ;
; |8count:inst| ; 8 (0) ; 8 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 8 (0) ; 8 (0) ; 0 (0) ; |CHRONO|DiviseurDeFrequence:inst1|8count:inst ; work ;
; |f8count:sub| ; 8 (8) ; 8 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 8 (8) ; 8 (8) ; 0 (0) ; |CHRONO|DiviseurDeFrequence:inst1|8count:inst|f8count:sub ; work ;
; |sequenceur2:inst17| ; 1 (1) ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |CHRONO|sequenceur2:inst17 ; work ;
+--------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+---------------------------------------+
; Delay Chain Summary ;
+--------------+----------+-------------+
; Name ; Pin Type ; Pad to Core ;
+--------------+----------+-------------+
; BP1 ; Input ; OFF ;
; BP2 ; Input ; OFF ;
; H ; Input ; OFF ;
; A ; Output ; OFF ;
; Count ; Output ; OFF ;
; Reset ; Output ; OFF ;
; B ; Output ; OFF ;
; C ; Output ; OFF ;
; D ; Output ; OFF ;
; E ; Output ; OFF ;
; F ; Output ; OFF ;
; G ; Output ; OFF ;
; a1 ; Output ; OFF ;
; b1 ; Output ; OFF ;
; c1 ; Output ; OFF ;
; e1 ; Output ; OFF ;
; f1 ; Output ; OFF ;
; g1 ; Output ; OFF ;
; d1 ; Output ; OFF ;
; pointSeconde ; Output ; OFF ;
; pointDixieme ; Output ; OFF ;
; BP1out ; Output ; OFF ;
+--------------+----------+-------------+
+--------------+
; Pin-Out File ;
+--------------+
The pin-out file can be found in E:/SLEA/Chronometre.pin.
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Info: Processing started: Wed Jan 24 17:22:00 2018
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off Chronometre -c Chronometre
Info: Selected device EPF10K70RC240-4 for design "Chronometre"
Warning: Feature SignalProbe is not available with your current license
Info: Fitter is using the Classic Timing Analyzer
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Not setting a global tsu requirement
Info: Not setting a global tco requirement
Info: Not setting a global tpd requirement
Info: Inserted 1 logic cells in first fitting attempt
Info: Started fitting attempt 1 on Wed Jan 24 2018 at 17:22:01
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: Quartus II Fitter was successful. 0 errors, 1 warning
Info: Peak virtual memory: 194 megabytes
Info: Processing ended: Wed Jan 24 17:22:05 2018
Info: Elapsed time: 00:00:05
Info: Total CPU time (on all processors): 00:00:04

10
SLEA/Chronometre.fit.summary Normal file
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@ -0,0 +1,10 @@
Fitter Status : Successful - Wed Jan 24 17:22:04 2018
Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
Revision Name : Chronometre
Top-level Entity Name : CHRONO
Family : FLEX10K
Device : EPF10K70RC240-4
Timing Models : Final
Total logic elements : 70 / 3,744 ( 2 % )
Total pins : 22 / 189 ( 12 % )
Total memory bits : 0 / 18,432 ( 0 % )

115
SLEA/Chronometre.flow.rpt Normal file
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@ -0,0 +1,115 @@
Flow report for Chronometre
Wed Jan 24 17:22:10 2018
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Flow Summary
3. Flow Settings
4. Flow Non-Default Global Settings
5. Flow Elapsed Time
6. Flow OS Summary
7. Flow Log
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+------------------------------------------------------------------------+
; Flow Summary ;
+-------------------------+----------------------------------------------+
; Flow Status ; Successful - Wed Jan 24 17:22:10 2018 ;
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
; Revision Name ; Chronometre ;
; Top-level Entity Name ; CHRONO ;
; Family ; FLEX10K ;
; Device ; EPF10K70RC240-4 ;
; Timing Models ; Final ;
; Met timing requirements ; Yes ;
; Total logic elements ; 70 / 3,744 ( 2 % ) ;
; Total pins ; 22 / 189 ( 12 % ) ;
; Total memory bits ; 0 / 18,432 ( 0 % ) ;
+-------------------------+----------------------------------------------+
+-----------------------------------------+
; Flow Settings ;
+-------------------+---------------------+
; Option ; Setting ;
+-------------------+---------------------+
; Start date & time ; 01/24/2018 17:21:56 ;
; Main task ; Compilation ;
; Revision Name ; Chronometre ;
+-------------------+---------------------+
+------------------------------------------------------------------------------------------------------------------+
; Flow Non-Default Global Settings ;
+------------------------------------+------------------------------+---------------+-------------+----------------+
; Assignment Name ; Value ; Default Value ; Entity Name ; Section Id ;
+------------------------------------+------------------------------+---------------+-------------+----------------+
; COMPILER_SIGNATURE_ID ; 150930028222.151681091605568 ; -- ; -- ; -- ;
; MAX_CORE_JUNCTION_TEMP ; 85 ; -- ; -- ; -- ;
; MIN_CORE_JUNCTION_TEMP ; 0 ; -- ; -- ; -- ;
; MISC_FILE ; U:/SLEA/Chronometre.dpf ; -- ; -- ; -- ;
; SMART_RECOMPILE ; On ; Off ; -- ; -- ;
; TOP_LEVEL_ENTITY ; CHRONO ; Chronometre ; -- ; -- ;
; USE_GENERATED_PHYSICAL_CONSTRAINTS ; Off ; -- ; -- ; eda_blast_fpga ;
+------------------------------------+------------------------------+---------------+-------------+----------------+
+-----------------------------------------------------------------------------------------------------------------------------+
; Flow Elapsed Time ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Module Name ; Elapsed Time ; Average Processors Used ; Peak Virtual Memory ; Total CPU Time (on all processors) ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
; Analysis & Synthesis ; 00:00:03 ; 1.0 ; 199 MB ; 00:00:02 ;
; Fitter ; 00:00:04 ; 1.0 ; 175 MB ; 00:00:04 ;
; Assembler ; 00:00:01 ; 1.0 ; 176 MB ; 00:00:01 ;
; Classic Timing Analyzer ; 00:00:01 ; 1.0 ; 145 MB ; 00:00:00 ;
; Total ; 00:00:09 ; -- ; -- ; 00:00:07 ;
+-------------------------+--------------+-------------------------+---------------------+------------------------------------+
+------------------------------------------------------------------------------------------+
; Flow OS Summary ;
+-------------------------+------------------+---------------+------------+----------------+
; Module Name ; Machine Hostname ; OS Name ; OS Version ; Processor type ;
+-------------------------+------------------+---------------+------------+----------------+
; Analysis & Synthesis ; MFIN05 ; Windows Vista ; 6.1 ; i686 ;
; Fitter ; MFIN05 ; Windows Vista ; 6.1 ; i686 ;
; Assembler ; MFIN05 ; Windows Vista ; 6.1 ; i686 ;
; Classic Timing Analyzer ; MFIN05 ; Windows Vista ; 6.1 ; i686 ;
+-------------------------+------------------+---------------+------------+----------------+
------------
; Flow Log ;
------------
quartus_map --read_settings_files=on --write_settings_files=off Chronometre -c Chronometre
quartus_fit --read_settings_files=off --write_settings_files=off Chronometre -c Chronometre
quartus_asm --read_settings_files=off --write_settings_files=off Chronometre -c Chronometre
quartus_tan --read_settings_files=off --write_settings_files=off Chronometre -c Chronometre

280
SLEA/Chronometre.map.rpt Normal file
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@ -0,0 +1,280 @@
Analysis & Synthesis report for Chronometre
Wed Jan 24 17:21:59 2018
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. General Register Statistics
8. Parameter Settings for User Entity Instance: DiviseurDeFrequence:inst1|8count:inst4
9. Parameter Settings for User Entity Instance: DiviseurDeFrequence:inst1|8count:inst
10. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+----------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Wed Jan 24 17:21:59 2018 ;
; Quartus II Version ; 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition ;
; Revision Name ; Chronometre ;
; Top-level Entity Name ; CHRONO ;
; Family ; FLEX10K ;
; Total logic elements ; 69 ;
; Total pins ; 22 ;
; Total memory bits ; 0 ;
+-----------------------------+----------------------------------------------+
+------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------+-----------------+---------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------+-----------------+---------------+
; Device ; EPF10K70RC240-4 ; ;
; Top-level entity name ; CHRONO ; Chronometre ;
; Family name ; FLEX10K ; Stratix II ;
; Use smart compilation ; On ; Off ;
; Use Generated Physical Constraints File ; Off ; ;
; Create Debugging Nodes for IP Cores ; Off ; Off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Safe State Machine ; Off ; Off ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Ignore Verilog initial constructs ; Off ; Off ;
; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; Parallel Synthesis ; Off ; Off ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Auto Implement in ROM ; Off ; Off ;
; Optimization Technique ; Area ; Area ;
; Carry Chain Length ; 32 ; 32 ;
; Cascade Chain Length ; 2 ; 2 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Auto ROM Replacement ; On ; On ;
; Auto RAM Replacement ; On ; On ;
; Auto Clock Enable Replacement ; On ; On ;
; Strict RAM Replacement ; Off ; Off ;
; Auto Resource Sharing ; Off ; Off ;
; Allow Any RAM Size For Recognition ; Off ; Off ;
; Allow Any ROM Size For Recognition ; Off ; Off ;
; Use LogicLock Constraints during Resource Balancing ; On ; On ;
; Ignore translate_off and synthesis_off directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
; HDL message level ; Level2 ; Level2 ;
; Suppress Register Optimization Related Messages ; Off ; Off ;
; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
; Block Design Naming ; Auto ; Auto ;
; Synthesis Effort ; Auto ; Auto ;
; Shift Register Replacement - Allow Asynchronous Clear Signal ; On ; On ;
; Analysis & Synthesis Message Level ; Medium ; Medium ;
+--------------------------------------------------------------+-----------------+---------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------+
; BoutonPoussoir2.bdf ; yes ; User Block Diagram/Schematic File ; E:/SLEA/BoutonPoussoir2.bdf ;
; DiviseurDeFrequence.bdf ; yes ; User Block Diagram/Schematic File ; E:/SLEA/DiviseurDeFrequence.bdf ;
; CheminDeDonnees.bdf ; yes ; User Block Diagram/Schematic File ; E:/SLEA/CheminDeDonnees.bdf ;
; CHRONO.bdf ; yes ; User Block Diagram/Schematic File ; E:/SLEA/CHRONO.bdf ;
; sequenceur2.bdf ; yes ; User Block Diagram/Schematic File ; E:/SLEA/sequenceur2.bdf ;
; 7446.bdf ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/others/maxplus2/7446.bdf ;
; 74168.bdf ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/others/maxplus2/74168.bdf ;
; 8count.tdf ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/others/maxplus2/8count.tdf ;
; aglobal.inc ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/megafunctions/aglobal.inc ;
; f8count.bdf ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/others/maxplus2/f8count.bdf ;
; 7456.bdf ; yes ; Megafunction ; c:/altera/90sp2/quartus/libraries/others/maxplus2/7456.bdf ;
+----------------------------------+-----------------+------------------------------------+---------------------------------------------------------------+
+----------------------------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+----------------------------------+
; Resource ; Usage ;
+-----------------------------------+----------------------------------+
; Total logic elements ; 69 ;
; Total combinational functions ; 67 ;
; -- Total 4-input functions ; 32 ;
; -- Total 3-input functions ; 8 ;
; -- Total 2-input functions ; 6 ;
; -- Total 1-input functions ; 13 ;
; -- Total 0-input functions ; 8 ;
; Total registers ; 37 ;
; Total logic cells in carry chains ; 17 ;
; I/O pins ; 22 ;
; Maximum fan-out node ; DiviseurDeFrequence:inst1|inst10 ;
; Maximum fan-out ; 18 ;
; Total fan-out ; 257 ;
; Average fan-out ; 2.82 ;
+-----------------------------------+----------------------------------+
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+--------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------+--------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
+--------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------+--------------+
; |CHRONO ; 69 (0) ; 37 ; 0 ; 22 ; 32 (0) ; 2 (0) ; 35 (0) ; 17 (0) ; 0 (0) ; |CHRONO ; work ;
; |BoutonPoussoir2:inst15| ; 3 (3) ; 2 ; 0 ; 0 ; 1 (1) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |CHRONO|BoutonPoussoir2:inst15 ; work ;
; |BoutonPoussoir2:inst16| ; 2 (2) ; 2 ; 0 ; 0 ; 0 (0) ; 1 (1) ; 1 (1) ; 0 (0) ; 0 (0) ; |CHRONO|BoutonPoussoir2:inst16 ; work ;
; |CheminDeDonnees:inst| ; 41 (0) ; 12 ; 0 ; 0 ; 29 (0) ; 0 (0) ; 12 (0) ; 0 (0) ; 0 (0) ; |CHRONO|CheminDeDonnees:inst ; work ;
; |74168:inst1| ; 10 (10) ; 4 ; 0 ; 0 ; 6 (6) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |CHRONO|CheminDeDonnees:inst|74168:inst1 ; work ;
; |74168:inst2| ; 8 (8) ; 4 ; 0 ; 0 ; 4 (4) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |CHRONO|CheminDeDonnees:inst|74168:inst2 ; work ;
; |74168:inst8| ; 9 (9) ; 4 ; 0 ; 0 ; 5 (5) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |CHRONO|CheminDeDonnees:inst|74168:inst8 ; work ;
; |7446:inst4| ; 7 (7) ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |CHRONO|CheminDeDonnees:inst|7446:inst4 ; work ;
; |7446:inst7| ; 7 (7) ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |CHRONO|CheminDeDonnees:inst|7446:inst7 ; work ;
; |DiviseurDeFrequence:inst1| ; 22 (1) ; 20 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 20 (1) ; 17 (0) ; 0 (0) ; |CHRONO|DiviseurDeFrequence:inst1 ; work ;
; |7456:inst7| ; 3 (3) ; 3 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 (0) ; |CHRONO|DiviseurDeFrequence:inst1|7456:inst7 ; work ;
; |8count:inst4| ; 10 (0) ; 8 ; 0 ; 0 ; 2 (0) ; 0 (0) ; 8 (0) ; 9 (0) ; 0 (0) ; |CHRONO|DiviseurDeFrequence:inst1|8count:inst4 ; work ;
; |f8count:sub| ; 10 (10) ; 8 ; 0 ; 0 ; 2 (2) ; 0 (0) ; 8 (8) ; 9 (9) ; 0 (0) ; |CHRONO|DiviseurDeFrequence:inst1|8count:inst4|f8count:sub ; work ;
; |8count:inst| ; 8 (0) ; 8 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 8 (0) ; 8 (0) ; 0 (0) ; |CHRONO|DiviseurDeFrequence:inst1|8count:inst ; work ;
; |f8count:sub| ; 8 (8) ; 8 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 8 (8) ; 8 (8) ; 0 (0) ; |CHRONO|DiviseurDeFrequence:inst1|8count:inst|f8count:sub ; work ;
; |sequenceur2:inst17| ; 1 (1) ; 1 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 1 (1) ; 0 (0) ; 0 (0) ; |CHRONO|sequenceur2:inst17 ; work ;
+--------------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 37 ;
; Number of registers using Synchronous Clear ; 7 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 0 ;
; Number of registers using Asynchronous Load ; 0 ;
; Number of registers using Clock Enable ; 1 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+-------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: DiviseurDeFrequence:inst1|8count:inst4 ;
+------------------------+---------+--------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+---------+--------------------------------------------------+
; DEVICE_FAMILY ; FLEX10K ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+---------+--------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: DiviseurDeFrequence:inst1|8count:inst ;
+------------------------+---------+-------------------------------------------------+
; Parameter Name ; Value ; Type ;
+------------------------+---------+-------------------------------------------------+
; DEVICE_FAMILY ; FLEX10K ; Untyped ;
; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
+------------------------+---------+-------------------------------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Info: Processing started: Wed Jan 24 17:21:56 2018
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Chronometre -c Chronometre
Info: Found 1 design units, including 1 entities, in source file Decodeur.bdf
Info: Found entity 1: Decodeur
Info: Found 1 design units, including 1 entities, in source file BoutonPoussoir.bdf
Info: Found entity 1: BoutonPoussoir
Info: Found 1 design units, including 1 entities, in source file BoutonPoussoir2.bdf
Info: Found entity 1: BoutonPoussoir2
Info: Found 1 design units, including 1 entities, in source file DiviseurDeFrequence.bdf
Info: Found entity 1: DiviseurDeFrequence
Info: Found 1 design units, including 1 entities, in source file CheminDeDonnees.bdf
Info: Found entity 1: CheminDeDonnees
Warning: Can't analyze file -- file E:/SLEA/Sequenceur.bdf is missing
Info: Found 1 design units, including 1 entities, in source file CHRONO.bdf
Info: Found entity 1: CHRONO
Info: Found 1 design units, including 1 entities, in source file sequenceur2.bdf
Info: Found entity 1: sequenceur2
Info: Elaborating entity "CHRONO" for the top level hierarchy
Info: Elaborating entity "CheminDeDonnees" for hierarchy "CheminDeDonnees:inst"
Info: Elaborating entity "7446" for hierarchy "CheminDeDonnees:inst|7446:inst7"
Info: Elaborated megafunction instantiation "CheminDeDonnees:inst|7446:inst7"
Info: Elaborating entity "74168" for hierarchy "CheminDeDonnees:inst|74168:inst2"
Info: Elaborated megafunction instantiation "CheminDeDonnees:inst|74168:inst2"
Info: Elaborating entity "DiviseurDeFrequence" for hierarchy "DiviseurDeFrequence:inst1"
Info: Elaborating entity "8count" for hierarchy "DiviseurDeFrequence:inst1|8count:inst4"
Info: Elaborated megafunction instantiation "DiviseurDeFrequence:inst1|8count:inst4"
Info: Elaborating entity "f8count" for hierarchy "DiviseurDeFrequence:inst1|8count:inst4|f8count:sub"
Info: Elaborated megafunction instantiation "DiviseurDeFrequence:inst1|8count:inst4|f8count:sub", which is child of megafunction instantiation "DiviseurDeFrequence:inst1|8count:inst4"
Info: Elaborating entity "8count" for hierarchy "DiviseurDeFrequence:inst1|8count:inst"
Info: Elaborated megafunction instantiation "DiviseurDeFrequence:inst1|8count:inst"
Info: Elaborating entity "7456" for hierarchy "DiviseurDeFrequence:inst1|7456:inst7"
Info: Elaborated megafunction instantiation "DiviseurDeFrequence:inst1|7456:inst7"
Info: Elaborating entity "sequenceur2" for hierarchy "sequenceur2:inst17"
Info: Elaborating entity "BoutonPoussoir2" for hierarchy "BoutonPoussoir2:inst15"
Warning: Output pins are stuck at VCC or GND
Warning (13410): Pin "pointSeconde" is stuck at VCC
Warning (13410): Pin "pointDixieme" is stuck at GND
Info: Converted 2 single input CARRY primitives to CARRY_SUM primitives
Info: Implemented 91 device resources after synthesis - the final resource count might be different
Info: Implemented 3 input pins
Info: Implemented 19 output pins
Info: Implemented 69 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings
Info: Peak virtual memory: 199 megabytes
Info: Processing ended: Wed Jan 24 17:21:59 2018
Info: Elapsed time: 00:00:03
Info: Total CPU time (on all processors): 00:00:02

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Analysis & Synthesis Status : Successful - Wed Jan 24 17:21:59 2018
Quartus II Version : 9.0 Build 235 06/17/2009 SP 2 SJ Web Edition
Revision Name : Chronometre
Top-level Entity Name : CHRONO
Family : FLEX10K
Total logic elements : 69
Total pins : 22
Total memory bits : 0

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-- Copyright (C) 1991-2009 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions
-- and other software and tools, and its AMPP partner logic
-- functions, and any output files from any of the foregoing
-- (including device programming or simulation files), and any
-- associated documentation or information are expressly subject
-- to the terms and conditions of the Altera Program License
-- Subscription Agreement, Altera MegaCore Function License
-- Agreement, or other applicable license agreement, including,
-- without limitation, that your use is for the sole purpose of
-- programming logic devices manufactured by Altera and sold by
-- Altera or its authorized distributors. Please refer to the
-- applicable agreement for further details.
--
-- This is a Quartus II output file. It is for reporting purposes only, and is
-- not intended for use as a Quartus II input file. This file cannot be used
-- to make Quartus II pin assignments - for instructions on how to make pin
-- assignments, please see Quartus II help.
------------------------------------------------------------------------------
------------------------------------------------------------------------------
-- NC : No Connect. This pin has no internal connection to the device.
-- VCC_INT : Dedicated power pin, which MUST be connected to VCC (5.0V).
-- VCC_IO : Dedicated power pin, which MUST be connected to VCC (Refer to
-- the table below for voltage).
-- GND : Dedicated ground pin, which MUST be connected to GND.
-- GND+ : Unused input. This pin should be connected to GND. It may also
-- be connected to a valid signal on the board (low, high, or
-- toggling) if that signal is required for a different revision
-- of the design.
-- GND* : Unused I/O pin. This pin can either be left unconnected or
-- connected to GND. Connecting this pin to GND will improve the
-- device's immunity to noise.
------------------------------------------------------------------------------
File Generation Date & Time: Wed Jan 24 17:22:04 2018
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
CHIP "Chronometre" ASSIGNED TO AN: EPF10K70RC240-4
Pin Name/Usage : Location : Dir. : I/O Standard : Voltage : I/O Bank : User Assignment
-------------------------------------------------------------------------------------------------------------
TCK : 1 : input : : : :
CONF_DONE : 2 : bidir : : : :
nCEO : 3 : output : : : :
TDO : 4 : output : : : :
VCC_INT : 5 : power : : 5.0V : :
A : 6 : output : TTL : : : Y
B : 7 : output : TTL : : : Y
C : 8 : output : TTL : : : Y
D : 9 : output : TTL : : : Y
GND_INT : 10 : gnd : : : :
E : 11 : output : TTL : : : Y
F : 12 : output : TTL : : : Y
G : 13 : output : TTL : : : Y
pointDixieme : 14 : output : TTL : : : Y
GND* : 15 : : : : :
VCC_INT : 16 : power : : 5.0V : :
a1 : 17 : output : TTL : : : Y
b1 : 18 : output : TTL : : : Y
c1 : 19 : output : TTL : : : Y
d1 : 20 : output : TTL : : : Y
e1 : 21 : output : TTL : : : Y
GND_INT : 22 : gnd : : : :
f1 : 23 : output : TTL : : : Y
g1 : 24 : output : TTL : : : Y
pointSeconde : 25 : output : TTL : : : Y
GND* : 26 : : : : :
VCC_INT : 27 : power : : 5.0V : :
BP1 : 28 : input : TTL : : : Y
BP2 : 29 : input : TTL : : : Y
GND* : 30 : : : : :
GND* : 31 : : : : :
GND_INT : 32 : gnd : : : :
GND* : 33 : : : : :
GND* : 34 : : : : :
GND* : 35 : : : : :
GND* : 36 : : : : :
VCC_INT : 37 : power : : 5.0V : :
GND* : 38 : : : : :
GND* : 39 : : : : :
GND* : 40 : : : : :
GND* : 41 : : : : :
GND_INT : 42 : gnd : : : :
GND* : 43 : : : : :
GND* : 44 : : : : :
BP1out : 45 : output : TTL : : : Y
GND* : 46 : : : : :
VCC_INT : 47 : power : : 5.0V : :
Count : 48 : output : TTL : : : Y
GND* : 49 : : : : :
GND* : 50 : : : : :
GND* : 51 : : : : :
GND_INT : 52 : gnd : : : :
Reset : 53 : output : TTL : : : Y
GND* : 54 : : : : :
GND* : 55 : : : : :
GND* : 56 : : : : :
VCC_INT : 57 : power : : 5.0V : :
TMS : 58 : input : : : :
TRST : 59 : input : : : :
nSTATUS : 60 : bidir : : : :
GND* : 61 : : : : :
GND* : 62 : : : : :
GND* : 63 : : : : :
GND* : 64 : : : : :
GND* : 65 : : : : :
GND* : 66 : : : : :
GND* : 67 : : : : :
GND* : 68 : : : : :
GND_INT : 69 : gnd : : : :
GND* : 70 : : : : :
GND* : 71 : : : : :
GND* : 72 : : : : :
GND* : 73 : : : : :
GND* : 74 : : : : :
GND* : 75 : : : : :
GND* : 76 : : : : :
VCC_INT : 77 : power : : 5.0V : :
GND* : 78 : : : : :
GND* : 79 : : : : :
GND* : 80 : : : : :
GND* : 81 : : : : :
GND* : 82 : : : : :
GND* : 83 : : : : :
GND* : 84 : : : : :
GND_INT : 85 : gnd : : : :
GND* : 86 : : : : :
GND* : 87 : : : : :
GND* : 88 : : : : :
VCC_INT : 89 : power : : 5.0V : :
GND+ : 90 : : : : :
H : 91 : input : TTL : : : Y
GND+ : 92 : : : : :
GND_INT : 93 : gnd : : : :
GND* : 94 : : : : :
GND* : 95 : : : : :
VCC_INT : 96 : power : : 5.0V : :
GND* : 97 : : : : :
GND* : 98 : : : : :
GND* : 99 : : : : :
GND* : 100 : : : : :
GND* : 101 : : : : :
GND* : 102 : : : : :
GND* : 103 : : : : :
GND_INT : 104 : gnd : : : :
GND* : 105 : : : : :
GND* : 106 : : : : :
GND* : 107 : : : : :
GND* : 108 : : : : :
GND* : 109 : : : : :
GND* : 110 : : : : :
GND* : 111 : : : : :
VCC_INT : 112 : power : : 5.0V : :
GND* : 113 : : : : :
GND* : 114 : : : : :
GND* : 115 : : : : :
GND* : 116 : : : : :
GND* : 117 : : : : :
GND* : 118 : : : : :
GND* : 119 : : : : :
GND* : 120 : : : : :
nCONFIG : 121 : input : : : :
VCC_INT : 122 : power : : 5.0V : :
MSEL1 : 123 : input : : : :
MSEL0 : 124 : input : : : :
GND_INT : 125 : gnd : : : :
GND* : 126 : : : : :
GND* : 127 : : : : :
GND* : 128 : : : : :
GND* : 129 : : : : :
VCC_INT : 130 : power : : 5.0V : :
GND* : 131 : : : : :
GND* : 132 : : : : :
GND* : 133 : : : : :
GND* : 134 : : : : :
GND_INT : 135 : gnd : : : :
GND* : 136 : : : : :
GND* : 137 : : : : :
GND* : 138 : : : : :
GND* : 139 : : : : :
VCC_INT : 140 : power : : 5.0V : :
GND* : 141 : : : : :
GND* : 142 : : : : :
GND* : 143 : : : : :
GND* : 144 : : : : :
GND_INT : 145 : gnd : : : :
GND* : 146 : : : : :
GND* : 147 : : : : :
GND* : 148 : : : : :
GND* : 149 : : : : :
VCC_INT : 150 : power : : 5.0V : :
GND* : 151 : : : : :
GND* : 152 : : : : :
GND* : 153 : : : : :
GND* : 154 : : : : :
GND_INT : 155 : gnd : : : :
GND* : 156 : : : : :
GND* : 157 : : : : :
GND* : 158 : : : : :
GND* : 159 : : : : :
VCC_INT : 160 : power : : 5.0V : :
GND* : 161 : : : : :
GND* : 162 : : : : :
GND* : 163 : : : : :
GND* : 164 : : : : :
GND_INT : 165 : gnd : : : :
GND* : 166 : : : : :
GND* : 167 : : : : :
GND* : 168 : : : : :
GND* : 169 : : : : :
VCC_INT : 170 : power : : 5.0V : :
GND* : 171 : : : : :
GND* : 172 : : : : :
GND* : 173 : : : : :
GND* : 174 : : : : :
GND* : 175 : : : : :
GND_INT : 176 : gnd : : : :
TDI : 177 : input : : : :
nCE : 178 : input : : : :
DCLK : 179 : bidir : : : :
DATA0 : 180 : input : : : :
GND* : 181 : : : : :
GND* : 182 : : : : :
GND* : 183 : : : : :
GND* : 184 : : : : :
GND* : 185 : : : : :
GND* : 186 : : : : :
GND* : 187 : : : : :
GND* : 188 : : : : :
VCC_INT : 189 : power : : 5.0V : :
GND* : 190 : : : : :
GND* : 191 : : : : :
GND* : 192 : : : : :
GND* : 193 : : : : :
GND* : 194 : : : : :
GND* : 195 : : : : :
GND* : 196 : : : : :
GND_INT : 197 : gnd : : : :
GND* : 198 : : : : :
GND* : 199 : : : : :
GND* : 200 : : : : :
GND* : 201 : : : : :
GND* : 202 : : : : :
GND* : 203 : : : : :
GND* : 204 : : : : :
VCC_INT : 205 : power : : 5.0V : :
GND* : 206 : : : : :
GND* : 207 : : : : :
GND* : 208 : : : : :
GND* : 209 : : : : :
GND+ : 210 : : : : :
GND+ : 211 : : : : :
GND+ : 212 : : : : :
GND* : 213 : : : : :
GND* : 214 : : : : :
GND* : 215 : : : : :
GND_INT : 216 : gnd : : : :
GND* : 217 : : : : :
GND* : 218 : : : : :
GND* : 219 : : : : :
GND* : 220 : : : : :
GND* : 221 : : : : :
GND* : 222 : : : : :
GND* : 223 : : : : :
VCC_INT : 224 : power : : 5.0V : :
GND* : 225 : : : : :
GND* : 226 : : : : :
GND* : 227 : : : : :
GND* : 228 : : : : :
GND* : 229 : : : : :
GND* : 230 : : : : :
GND* : 231 : : : : :
GND_INT : 232 : gnd : : : :
GND* : 233 : : : : :
GND* : 234 : : : : :
GND* : 235 : : : : :
GND* : 236 : : : : :
GND* : 237 : : : : :
GND* : 238 : : : : :
GND* : 239 : : : : :
GND* : 240 : : : : :

BIN
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
# Date created = 13:44:11 December 08, 2017
#
# -------------------------------------------------------------------------- #
QUARTUS_VERSION = "9.0"
DATE = "13:44:11 December 08, 2017"
# Revisions
PROJECT_REVISION = "Chronometre"

86
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# -------------------------------------------------------------------------- #
#
# Copyright (C) 1991-2009 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions
# and other software and tools, and its AMPP partner logic
# functions, and any output files from any of the foregoing
# (including device programming or simulation files), and any
# associated documentation or information are expressly subject
# to the terms and conditions of the Altera Program License
# Subscription Agreement, Altera MegaCore Function License
# Agreement, or other applicable license agreement, including,
# without limitation, that your use is for the sole purpose of
# programming logic devices manufactured by Altera and sold by
# Altera or its authorized distributors. Please refer to the
# applicable agreement for further details.
#
# -------------------------------------------------------------------------- #
#
# Quartus II
# Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
# Date created = 13:44:11 December 08, 2017
#
# -------------------------------------------------------------------------- #
#
# Notes:
#
# 1) The default values for assignments are stored in the file:
# Chronometre_assignment_defaults.qdf
# If this file doesn't exist, see file:
# assignment_defaults.qdf
#
# 2) Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.
#
# -------------------------------------------------------------------------- #
set_global_assignment -name FAMILY FLEX10K
set_global_assignment -name DEVICE "EPF10K70RC240-4"
set_global_assignment -name TOP_LEVEL_ENTITY CHRONO
set_global_assignment -name ORIGINAL_QUARTUS_VERSION "9.0 SP2"
set_global_assignment -name PROJECT_CREATION_TIME_DATE "13:44:11 DECEMBER 08, 2017"
set_global_assignment -name LAST_QUARTUS_VERSION "9.0 SP2"
set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85
set_global_assignment -name BDF_FILE Decodeur.bdf
set_global_assignment -name SMART_RECOMPILE ON
set_global_assignment -name FLEX10K_DEVICE_IO_STANDARD TTL
set_global_assignment -name MISC_FILE "U:/SLEA/Chronometre.dpf"
set_global_assignment -name VECTOR_WAVEFORM_FILE decodeur1.vwf
set_global_assignment -name SIMULATION_MODE FUNCTIONAL
set_global_assignment -name BDF_FILE BoutonPoussoir.bdf
set_global_assignment -name VECTOR_WAVEFORM_FILE BoutonPoussoir.vwf
set_global_assignment -name BDF_FILE BoutonPoussoir2.bdf
set_global_assignment -name VECTOR_WAVEFORM_FILE BoutonPoussoir2.vwf
set_global_assignment -name BDF_FILE DiviseurDeFrequence.bdf
set_global_assignment -name BDF_FILE CheminDeDonnees.bdf
set_location_assignment PIN_6 -to A
set_location_assignment PIN_7 -to B
set_location_assignment PIN_8 -to C
set_location_assignment PIN_9 -to D
set_location_assignment PIN_11 -to E
set_location_assignment PIN_12 -to F
set_location_assignment PIN_13 -to G
set_location_assignment PIN_25 -to pointSeconde
set_location_assignment PIN_14 -to pointDixieme
set_location_assignment PIN_17 -to a1
set_location_assignment PIN_18 -to b1
set_location_assignment PIN_19 -to c1
set_location_assignment PIN_20 -to d1
set_location_assignment PIN_21 -to e1
set_location_assignment PIN_23 -to f1
set_location_assignment PIN_24 -to g1
set_global_assignment -name BDF_FILE Sequenceur.bdf
set_global_assignment -name BDF_FILE CHRONO.bdf
set_location_assignment PIN_91 -to H
set_location_assignment PIN_28 -to BP1
set_location_assignment PIN_29 -to BP2
set_location_assignment PIN_48 -to Count
set_location_assignment PIN_53 -to Reset
set_location_assignment PIN_45 -to BP1out
set_global_assignment -name BDF_FILE sequenceur2.bdf
set_global_assignment -name VECTOR_WAVEFORM_FILE sequenceur2.vwf
set_global_assignment -name INCREMENTAL_VECTOR_INPUT_SOURCE sequenceur2.vwf

17
SLEA/Chronometre.qws Normal file
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@ -0,0 +1,17 @@
[ProjectWorkspace]
ptn_Child1=Frames
[ProjectWorkspace.Frames]
ptn_Child1=ChildFrames
[ProjectWorkspace.Frames.ChildFrames]
ptn_Child1=Document-0
ptn_Child2=Document-1
ptn_Child3=Document-2
ptn_Child4=Document-3
[ProjectWorkspace.Frames.ChildFrames.Document-0]
ptn_Child1=ViewFrame-0
[ProjectWorkspace.Frames.ChildFrames.Document-0.ViewFrame-0]
DocPathName=CHRONO.bdf
DocumentCLSID={7b19e8f2-2bbe-11d1-a082-0020affa5bde}
IsChildFrameDetached=False
IsActiveChildFrame=False
ptn_Child1=StateMap

171
SLEA/Chronometre.sim.rpt Normal file
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@ -0,0 +1,171 @@
Simulator report for Chronometre
Wed Jan 24 16:29:12 2018
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Simulator Summary
3. Simulator Settings
4. Simulation Waveforms
5. Coverage Summary
6. Complete 1/0-Value Coverage
7. Missing 1-Value Coverage
8. Missing 0-Value Coverage
9. Simulator INI Usage
10. Simulator Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+--------------------------------------------+
; Simulator Summary ;
+-----------------------------+--------------+
; Type ; Value ;
+-----------------------------+--------------+
; Simulation Start Time ; 0 ps ;
; Simulation End Time ; 100.0 ms ;
; Simulation Netlist Size ; 8 nodes ;
; Simulation Coverage ; 100.00 % ;
; Total Number of Transitions ; 57 ;
; Simulation Breakpoints ; 0 ;
; Family ; FLEX10K ;
+-----------------------------+--------------+
+------------------------------------------------------------------------------------------------------------------------------+
; Simulator Settings ;
+--------------------------------------------------------------------------------------------+-----------------+---------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------------------------------+-----------------+---------------+
; Simulation mode ; Functional ; Timing ;
; Start time ; 0 ns ; 0 ns ;
; Simulation results format ; CVWF ; ;
; Vector input source ; sequenceur2.vwf ; ;
; Add pins automatically to simulation output waveforms ; On ; On ;
; Check outputs ; Off ; Off ;
; Report simulation coverage ; On ; On ;
; Display complete 1/0 value coverage report ; On ; On ;
; Display missing 1-value coverage report ; On ; On ;
; Display missing 0-value coverage report ; On ; On ;
; Detect setup and hold time violations ; Off ; Off ;
; Detect glitches ; Off ; Off ;
; Disable timing delays in Timing Simulation ; Off ; Off ;
; Generate Signal Activity File ; Off ; Off ;
; Generate VCD File for PowerPlay Power Analyzer ; Off ; Off ;
; Group bus channels in simulation results ; Off ; Off ;
; Preserve fewer signal transitions to reduce memory requirements ; On ; On ;
; Trigger vector comparison with the specified mode ; INPUT_EDGE ; INPUT_EDGE ;
; Disable setup and hold time violations detection in input registers of bi-directional pins ; Off ; Off ;
; Overwrite Waveform Inputs With Simulation Outputs ; On ; ;
; Perform Glitch Filtering in Timing Simulation ; Auto ; Auto ;
+--------------------------------------------------------------------------------------------+-----------------+---------------+
+----------------------+
; Simulation Waveforms ;
+----------------------+
Waveform report data cannot be output to ASCII.
Please use Quartus II to view the waveform report data.
+--------------------------------------------------------------------+
; Coverage Summary ;
+-----------------------------------------------------+--------------+
; Type ; Value ;
+-----------------------------------------------------+--------------+
; Total coverage as a percentage ; 100.00 % ;
; Total nodes checked ; 8 ;
; Total output ports checked ; 8 ;
; Total output ports with complete 1/0-value coverage ; 8 ;
; Total output ports with no 1/0-value coverage ; 0 ;
; Total output ports with no 1-value coverage ; 0 ;
; Total output ports with no 0-value coverage ; 0 ;
+-----------------------------------------------------+--------------+
The following table displays output ports that toggle between 1 and 0 during simulation.
+------------------------------------------------------------+
; Complete 1/0-Value Coverage ;
+--------------------+--------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+--------------------+--------------------+------------------+
; |sequenceur2|COUNT ; |sequenceur2|COUNT ; pin_out ;
; |sequenceur2|inst3 ; |sequenceur2|inst3 ; regout ;
; |sequenceur2|H ; |sequenceur2|H ; out ;
; |sequenceur2|inst2 ; |sequenceur2|inst2 ; out0 ;
; |sequenceur2|sbp1 ; |sequenceur2|sbp1 ; out ;
; |sequenceur2|inst1 ; |sequenceur2|inst1 ; out0 ;
; |sequenceur2|sbp2 ; |sequenceur2|sbp2 ; out ;
; |sequenceur2|RESET ; |sequenceur2|RESET ; pin_out ;
+--------------------+--------------------+------------------+
The following table displays output ports that do not toggle to 1 during simulation.
+-------------------------------------------------+
; Missing 1-Value Coverage ;
+-----------+------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-----------+------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+-------------------------------------------------+
; Missing 0-Value Coverage ;
+-----------+------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-----------+------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Info: Processing started: Wed Jan 24 16:29:11 2018
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off Chronometre -c Chronometre
Info: Using vector source file "U:/SLEA/sequenceur2.vwf"
Info: Overwriting simulation input file with simulation results
Info: A backup of sequenceur2.vwf called Chronometre.sim_ori.vwf has been created in the db folder
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Warning: Found clock-sensitive change during active clock edge at time 10.0 ms on register "|sequenceur2|inst3"
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is 100.00 %
Info: Number of transitions in simulation is 57
Info: Vector file sequenceur2.vwf is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help.
Info: Quartus II Simulator was successful. 0 errors, 1 warning
Info: Peak virtual memory: 134 megabytes
Info: Processing ended: Wed Jan 24 16:29:12 2018
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01

BIN
SLEA/Chronometre.sof Normal file
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Binary file not shown.

503
SLEA/Chronometre.tan.rpt Normal file
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@ -0,0 +1,503 @@
Classic Timing Analyzer report for Chronometre
Wed Jan 24 17:22:10 2018
Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Timing Analyzer Summary
3. Timing Analyzer Settings
4. Clock Settings Summary
5. Parallel Compilation
6. Clock Setup: 'H'
7. tsu
8. tco
9. th
10. Timing Analyzer Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary ;
+------------------------------+-------+---------------+----------------------------------+-----------------------------------------------------+------------------------------------------------------+------------+----------+--------------+
; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+-------+---------------+----------------------------------+-----------------------------------------------------+------------------------------------------------------+------------+----------+--------------+
; Worst-case tsu ; N/A ; None ; 0.100 ns ; BP2 ; BoutonPoussoir2:inst16|inst ; -- ; H ; 0 ;
; Worst-case tco ; N/A ; None ; 40.800 ns ; CheminDeDonnees:inst|74168:inst1|49 ; a1 ; H ; -- ; 0 ;
; Worst-case th ; N/A ; None ; 5.700 ns ; BP1 ; BoutonPoussoir2:inst15|inst ; -- ; H ; 0 ;
; Clock Setup: 'H' ; N/A ; None ; 42.02 MHz ( period = 23.800 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; H ; H ; 0 ;
; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
+------------------------------+-------+---------------+----------------------------------+-----------------------------------------------------+------------------------------------------------------+------------+----------+--------------+
+--------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Settings ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Option ; Setting ; From ; To ; Entity Name ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
; Device Name ; EPF10K70RC240-4 ; ; ; ;
; Timing Models ; Final ; ; ; ;
; Default hold multicycle ; Same as Multicycle ; ; ; ;
; Cut paths between unrelated clock domains ; On ; ; ; ;
; Cut off read during write signal paths ; On ; ; ; ;
; Cut off feedback from I/O pins ; On ; ; ; ;
; Report Combined Fast/Slow Timing ; Off ; ; ; ;
; Ignore Clock Settings ; Off ; ; ; ;
; Analyze latches as synchronous elements ; On ; ; ; ;
; Enable Recovery/Removal analysis ; Off ; ; ; ;
; Enable Clock Latency ; Off ; ; ; ;
; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
; Minimum Core Junction Temperature ; 0 ; ; ; ;
; Maximum Core Junction Temperature ; 85 ; ; ; ;
; Number of source nodes to report per destination node ; 10 ; ; ; ;
; Number of destination nodes to report ; 10 ; ; ; ;
; Number of paths to report ; 200 ; ; ; ;
; Report Minimum Timing Checks ; Off ; ; ; ;
; Use Fast Timing Models ; Off ; ; ; ;
; Report IO Paths Separately ; Off ; ; ; ;
; Perform Multicorner Analysis ; Off ; ; ; ;
; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;
; Output I/O Timing Endpoint ; Near End ; ; ; ;
+---------------------------------------------------------------------+--------------------+------+----+-------------+
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; H ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
+-------------------------------------+
; Parallel Compilation ;
+----------------------------+--------+
; Processors ; Number ;
+----------------------------+--------+
; Number detected on machine ; 2 ;
; Maximum allowed ; 1 ;
+----------------------------+--------+
+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'H' ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A ; 42.02 MHz ( period = 23.800 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; H ; H ; None ; None ; 19.700 ns ;
; N/A ; 42.02 MHz ( period = 23.800 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; H ; H ; None ; None ; 19.700 ns ;
; N/A ; 42.37 MHz ( period = 23.600 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; H ; H ; None ; None ; 19.600 ns ;
; N/A ; 42.37 MHz ( period = 23.600 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; H ; H ; None ; None ; 19.600 ns ;
; N/A ; 42.37 MHz ( period = 23.600 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; H ; H ; None ; None ; 19.600 ns ;
; N/A ; 42.55 MHz ( period = 23.500 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; H ; H ; None ; None ; 19.400 ns ;
; N/A ; 42.55 MHz ( period = 23.500 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; H ; H ; None ; None ; 19.400 ns ;
; N/A ; 42.92 MHz ( period = 23.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; H ; H ; None ; None ; 19.300 ns ;
; N/A ; 42.92 MHz ( period = 23.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; H ; H ; None ; None ; 19.300 ns ;
; N/A ; 42.92 MHz ( period = 23.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; H ; H ; None ; None ; 19.300 ns ;
; N/A ; 43.10 MHz ( period = 23.200 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; H ; H ; None ; None ; 19.100 ns ;
; N/A ; 43.10 MHz ( period = 23.200 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; H ; H ; None ; None ; 19.100 ns ;
; N/A ; 43.48 MHz ( period = 23.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; H ; H ; None ; None ; 19.000 ns ;
; N/A ; 43.48 MHz ( period = 23.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; H ; H ; None ; None ; 19.000 ns ;
; N/A ; 43.48 MHz ( period = 23.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; H ; H ; None ; None ; 19.000 ns ;
; N/A ; 43.67 MHz ( period = 22.900 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; H ; H ; None ; None ; 18.800 ns ;
; N/A ; 43.67 MHz ( period = 22.900 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; H ; H ; None ; None ; 18.800 ns ;
; N/A ; 44.05 MHz ( period = 22.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; H ; H ; None ; None ; 18.700 ns ;
; N/A ; 44.05 MHz ( period = 22.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; H ; H ; None ; None ; 18.700 ns ;
; N/A ; 44.05 MHz ( period = 22.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; H ; H ; None ; None ; 18.700 ns ;
; N/A ; 46.51 MHz ( period = 21.500 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; H ; H ; None ; None ; 17.400 ns ;
; N/A ; 46.51 MHz ( period = 21.500 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; H ; H ; None ; None ; 17.400 ns ;
; N/A ; 46.95 MHz ( period = 21.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; H ; H ; None ; None ; 17.300 ns ;
; N/A ; 46.95 MHz ( period = 21.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; H ; H ; None ; None ; 17.300 ns ;
; N/A ; 46.95 MHz ( period = 21.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; H ; H ; None ; None ; 17.300 ns ;
; N/A ; 47.17 MHz ( period = 21.200 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; H ; H ; None ; None ; 17.100 ns ;
; N/A ; 47.17 MHz ( period = 21.200 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; H ; H ; None ; None ; 17.100 ns ;
; N/A ; 47.17 MHz ( period = 21.200 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; H ; H ; None ; None ; 17.200 ns ;
; N/A ; 47.17 MHz ( period = 21.200 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; H ; H ; None ; None ; 17.200 ns ;
; N/A ; 47.62 MHz ( period = 21.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; H ; H ; None ; None ; 17.000 ns ;
; N/A ; 47.62 MHz ( period = 21.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; H ; H ; None ; None ; 17.000 ns ;
; N/A ; 47.62 MHz ( period = 21.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; H ; H ; None ; None ; 17.000 ns ;
; N/A ; 47.85 MHz ( period = 20.900 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; H ; H ; None ; None ; 16.800 ns ;
; N/A ; 47.85 MHz ( period = 20.900 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; H ; H ; None ; None ; 16.800 ns ;
; N/A ; 47.85 MHz ( period = 20.900 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; H ; H ; None ; None ; 16.900 ns ;
; N/A ; 47.85 MHz ( period = 20.900 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; H ; H ; None ; None ; 16.900 ns ;
; N/A ; 48.31 MHz ( period = 20.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; H ; H ; None ; None ; 16.700 ns ;
; N/A ; 48.31 MHz ( period = 20.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; H ; H ; None ; None ; 16.700 ns ;
; N/A ; 48.31 MHz ( period = 20.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; H ; H ; None ; None ; 16.700 ns ;
; N/A ; 48.54 MHz ( period = 20.600 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; H ; H ; None ; None ; 16.500 ns ;
; N/A ; 48.54 MHz ( period = 20.600 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; H ; H ; None ; None ; 16.500 ns ;
; N/A ; 48.54 MHz ( period = 20.600 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; H ; H ; None ; None ; 16.600 ns ;
; N/A ; 48.54 MHz ( period = 20.600 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; H ; H ; None ; None ; 16.600 ns ;
; N/A ; 49.02 MHz ( period = 20.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; H ; H ; None ; None ; 16.400 ns ;
; N/A ; 49.02 MHz ( period = 20.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; H ; H ; None ; None ; 16.400 ns ;
; N/A ; 49.02 MHz ( period = 20.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; H ; H ; None ; None ; 16.400 ns ;
; N/A ; 49.26 MHz ( period = 20.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; H ; H ; None ; None ; 16.200 ns ;
; N/A ; 49.26 MHz ( period = 20.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; H ; H ; None ; None ; 16.200 ns ;
; N/A ; 49.26 MHz ( period = 20.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; H ; H ; None ; None ; 16.300 ns ;
; N/A ; 49.26 MHz ( period = 20.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; H ; H ; None ; None ; 16.300 ns ;
; N/A ; 49.75 MHz ( period = 20.100 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; H ; H ; None ; None ; 16.100 ns ;
; N/A ; 49.75 MHz ( period = 20.100 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; H ; H ; None ; None ; 16.100 ns ;
; N/A ; 49.75 MHz ( period = 20.100 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; H ; H ; None ; None ; 16.100 ns ;
; N/A ; 50.00 MHz ( period = 20.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; H ; H ; None ; None ; 15.900 ns ;
; N/A ; 50.00 MHz ( period = 20.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; H ; H ; None ; None ; 15.900 ns ;
; N/A ; 50.51 MHz ( period = 19.800 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; H ; H ; None ; None ; 15.800 ns ;
; N/A ; 50.51 MHz ( period = 19.800 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; H ; H ; None ; None ; 15.800 ns ;
; N/A ; 50.51 MHz ( period = 19.800 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; H ; H ; None ; None ; 15.800 ns ;
; N/A ; 50.76 MHz ( period = 19.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; H ; H ; None ; None ; 15.600 ns ;
; N/A ; 50.76 MHz ( period = 19.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; H ; H ; None ; None ; 15.600 ns ;
; N/A ; 51.28 MHz ( period = 19.500 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; H ; H ; None ; None ; 15.500 ns ;
; N/A ; 51.28 MHz ( period = 19.500 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; H ; H ; None ; None ; 15.500 ns ;
; N/A ; 51.28 MHz ( period = 19.500 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; H ; H ; None ; None ; 15.500 ns ;
; N/A ; 51.55 MHz ( period = 19.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; H ; H ; None ; None ; 15.300 ns ;
; N/A ; 51.55 MHz ( period = 19.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; H ; H ; None ; None ; 15.300 ns ;
; N/A ; 52.08 MHz ( period = 19.200 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; H ; H ; None ; None ; 15.200 ns ;
; N/A ; 52.08 MHz ( period = 19.200 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; H ; H ; None ; None ; 15.200 ns ;
; N/A ; 52.08 MHz ( period = 19.200 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; H ; H ; None ; None ; 15.200 ns ;
; N/A ; 52.91 MHz ( period = 18.900 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; H ; H ; None ; None ; 14.900 ns ;
; N/A ; 52.91 MHz ( period = 18.900 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; H ; H ; None ; None ; 14.900 ns ;
; N/A ; 53.76 MHz ( period = 18.600 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; H ; H ; None ; None ; 14.600 ns ;
; N/A ; 53.76 MHz ( period = 18.600 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; H ; H ; None ; None ; 14.600 ns ;
; N/A ; 54.64 MHz ( period = 18.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|5 ; H ; H ; None ; None ; 14.300 ns ;
; N/A ; 54.64 MHz ( period = 18.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|6 ; H ; H ; None ; None ; 14.300 ns ;
; N/A ; 54.64 MHz ( period = 18.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|8 ; H ; H ; None ; None ; 14.300 ns ;
; N/A ; 54.64 MHz ( period = 18.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; H ; H ; None ; None ; 14.300 ns ;
; N/A ; 54.64 MHz ( period = 18.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; H ; H ; None ; None ; 14.300 ns ;
; N/A ; 54.64 MHz ( period = 18.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; H ; H ; None ; None ; 14.300 ns ;
; N/A ; 54.64 MHz ( period = 18.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; H ; H ; None ; None ; 14.300 ns ;
; N/A ; 54.64 MHz ( period = 18.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; H ; H ; None ; None ; 14.300 ns ;
; N/A ; 54.64 MHz ( period = 18.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; H ; H ; None ; None ; 14.300 ns ;
; N/A ; 54.95 MHz ( period = 18.200 ns ) ; sequenceur2:inst17|inst3 ; CheminDeDonnees:inst|74168:inst2|49 ; H ; H ; None ; None ; 14.200 ns ;
; N/A ; 54.95 MHz ( period = 18.200 ns ) ; CheminDeDonnees:inst|74168:inst1|3 ; CheminDeDonnees:inst|74168:inst2|49 ; H ; H ; None ; None ; 14.200 ns ;
; N/A ; 54.95 MHz ( period = 18.200 ns ) ; CheminDeDonnees:inst|74168:inst8|49 ; CheminDeDonnees:inst|74168:inst2|49 ; H ; H ; None ; None ; 14.200 ns ;
; N/A ; 54.95 MHz ( period = 18.200 ns ) ; sequenceur2:inst17|inst3 ; CheminDeDonnees:inst|74168:inst2|29 ; H ; H ; None ; None ; 14.200 ns ;
; N/A ; 54.95 MHz ( period = 18.200 ns ) ; CheminDeDonnees:inst|74168:inst1|3 ; CheminDeDonnees:inst|74168:inst2|29 ; H ; H ; None ; None ; 14.200 ns ;
; N/A ; 54.95 MHz ( period = 18.200 ns ) ; CheminDeDonnees:inst|74168:inst8|49 ; CheminDeDonnees:inst|74168:inst2|29 ; H ; H ; None ; None ; 14.200 ns ;
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; DiviseurDeFrequence:inst1|inst10 ; H ; H ; None ; None ; 14.000 ns ;
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|5 ; H ; H ; None ; None ; 14.000 ns ;
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|6 ; H ; H ; None ; None ; 14.000 ns ;
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|8 ; H ; H ; None ; None ; 14.000 ns ;
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; H ; H ; None ; None ; 14.000 ns ;
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; H ; H ; None ; None ; 14.000 ns ;
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; H ; H ; None ; None ; 14.000 ns ;
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; H ; H ; None ; None ; 14.000 ns ;
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; H ; H ; None ; None ; 14.000 ns ;
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; H ; H ; None ; None ; 14.000 ns ;
; N/A ; 55.87 MHz ( period = 17.900 ns ) ; CheminDeDonnees:inst|74168:inst8|3 ; CheminDeDonnees:inst|74168:inst2|49 ; H ; H ; None ; None ; 13.900 ns ;
; N/A ; 55.87 MHz ( period = 17.900 ns ) ; CheminDeDonnees:inst|74168:inst8|3 ; CheminDeDonnees:inst|74168:inst2|29 ; H ; H ; None ; None ; 13.900 ns ;
; N/A ; 55.87 MHz ( period = 17.900 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; H ; H ; None ; None ; 13.900 ns ;
; N/A ; 55.87 MHz ( period = 17.900 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; H ; H ; None ; None ; 13.900 ns ;
; N/A ; 56.50 MHz ( period = 17.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; DiviseurDeFrequence:inst1|inst10 ; H ; H ; None ; None ; 13.700 ns ;
; N/A ; 56.50 MHz ( period = 17.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|5 ; H ; H ; None ; None ; 13.700 ns ;
; N/A ; 56.50 MHz ( period = 17.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|6 ; H ; H ; None ; None ; 13.700 ns ;
; N/A ; 56.50 MHz ( period = 17.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; H ; H ; None ; None ; 13.800 ns ;
; N/A ; 56.50 MHz ( period = 17.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|8 ; H ; H ; None ; None ; 13.700 ns ;
; N/A ; 56.50 MHz ( period = 17.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; H ; H ; None ; None ; 13.700 ns ;
; N/A ; 56.50 MHz ( period = 17.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; H ; H ; None ; None ; 13.800 ns ;
; N/A ; 56.50 MHz ( period = 17.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; H ; H ; None ; None ; 13.700 ns ;
; N/A ; 56.50 MHz ( period = 17.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; H ; H ; None ; None ; 13.800 ns ;
; N/A ; 56.50 MHz ( period = 17.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; H ; H ; None ; None ; 13.700 ns ;
; N/A ; 56.50 MHz ( period = 17.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; H ; H ; None ; None ; 13.700 ns ;
; N/A ; 56.50 MHz ( period = 17.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; H ; H ; None ; None ; 13.700 ns ;
; N/A ; 56.50 MHz ( period = 17.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; H ; H ; None ; None ; 13.700 ns ;
; N/A ; 56.82 MHz ( period = 17.600 ns ) ; BoutonPoussoir2:inst15|inst ; CheminDeDonnees:inst|74168:inst8|49 ; H ; H ; None ; None ; 13.600 ns ;
; N/A ; 56.82 MHz ( period = 17.600 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; H ; H ; None ; None ; 13.600 ns ;
; N/A ; 56.82 MHz ( period = 17.600 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; H ; H ; None ; None ; 13.600 ns ;
; N/A ; 57.47 MHz ( period = 17.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; DiviseurDeFrequence:inst1|inst10 ; H ; H ; None ; None ; 13.400 ns ;
; N/A ; 57.47 MHz ( period = 17.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|5 ; H ; H ; None ; None ; 13.400 ns ;
; N/A ; 57.47 MHz ( period = 17.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|6 ; H ; H ; None ; None ; 13.400 ns ;
; N/A ; 57.47 MHz ( period = 17.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; H ; H ; None ; None ; 13.500 ns ;
; N/A ; 57.47 MHz ( period = 17.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|8 ; H ; H ; None ; None ; 13.400 ns ;
; N/A ; 57.47 MHz ( period = 17.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; H ; H ; None ; None ; 13.400 ns ;
; N/A ; 57.47 MHz ( period = 17.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; H ; H ; None ; None ; 13.500 ns ;
; N/A ; 57.47 MHz ( period = 17.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; H ; H ; None ; None ; 13.400 ns ;
; N/A ; 57.47 MHz ( period = 17.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; H ; H ; None ; None ; 13.500 ns ;
; N/A ; 57.47 MHz ( period = 17.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; H ; H ; None ; None ; 13.400 ns ;
; N/A ; 57.47 MHz ( period = 17.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; H ; H ; None ; None ; 13.400 ns ;
; N/A ; 57.47 MHz ( period = 17.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; H ; H ; None ; None ; 13.400 ns ;
; N/A ; 57.47 MHz ( period = 17.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; H ; H ; None ; None ; 13.400 ns ;
; N/A ; 57.80 MHz ( period = 17.300 ns ) ; BoutonPoussoir2:inst15|inst5 ; CheminDeDonnees:inst|74168:inst8|49 ; H ; H ; None ; None ; 13.300 ns ;
; N/A ; 57.80 MHz ( period = 17.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; H ; H ; None ; None ; 13.300 ns ;
; N/A ; 57.80 MHz ( period = 17.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; H ; H ; None ; None ; 13.300 ns ;
; N/A ; 58.48 MHz ( period = 17.100 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; DiviseurDeFrequence:inst1|inst10 ; H ; H ; None ; None ; 13.100 ns ;
; N/A ; 58.48 MHz ( period = 17.100 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; H ; H ; None ; None ; 13.200 ns ;
; N/A ; 58.48 MHz ( period = 17.100 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; H ; H ; None ; None ; 13.200 ns ;
; N/A ; 58.48 MHz ( period = 17.100 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; H ; H ; None ; None ; 13.200 ns ;
; N/A ; 58.48 MHz ( period = 17.100 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; H ; H ; None ; None ; 13.100 ns ;
; N/A ; 58.48 MHz ( period = 17.100 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; H ; H ; None ; None ; 13.100 ns ;
; N/A ; 58.82 MHz ( period = 17.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|1 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; H ; H ; None ; None ; 13.000 ns ;
; N/A ; 58.82 MHz ( period = 17.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|1 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; H ; H ; None ; None ; 13.000 ns ;
; N/A ; 59.52 MHz ( period = 16.800 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|1 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; H ; H ; None ; None ; 12.900 ns ;
; N/A ; 59.52 MHz ( period = 16.800 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|1 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; H ; H ; None ; None ; 12.900 ns ;
; N/A ; 59.52 MHz ( period = 16.800 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|1 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; H ; H ; None ; None ; 12.900 ns ;
; N/A ; 59.52 MHz ( period = 16.800 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; H ; H ; None ; None ; 12.800 ns ;
; N/A ; 59.52 MHz ( period = 16.800 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; H ; H ; None ; None ; 12.800 ns ;
; N/A ; 62.50 MHz ( period = 16.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|1 ; H ; H ; None ; None ; 11.900 ns ;
; N/A ; 62.50 MHz ( period = 16.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|4 ; H ; H ; None ; None ; 11.900 ns ;
; N/A ; 62.50 MHz ( period = 16.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|5 ; H ; H ; None ; None ; 12.000 ns ;
; N/A ; 62.50 MHz ( period = 16.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|6 ; H ; H ; None ; None ; 12.000 ns ;
; N/A ; 62.50 MHz ( period = 16.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|8 ; H ; H ; None ; None ; 12.000 ns ;
; N/A ; 62.50 MHz ( period = 16.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; H ; H ; None ; None ; 12.000 ns ;
; N/A ; 62.50 MHz ( period = 16.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; H ; H ; None ; None ; 12.000 ns ;
; N/A ; 62.50 MHz ( period = 16.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; H ; H ; None ; None ; 12.000 ns ;
; N/A ; 62.50 MHz ( period = 16.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; H ; H ; None ; None ; 12.000 ns ;
; N/A ; 62.89 MHz ( period = 15.900 ns ) ; CheminDeDonnees:inst|74168:inst1|49 ; CheminDeDonnees:inst|74168:inst2|49 ; H ; H ; None ; None ; 11.900 ns ;
; N/A ; 62.89 MHz ( period = 15.900 ns ) ; CheminDeDonnees:inst|74168:inst1|49 ; CheminDeDonnees:inst|74168:inst2|29 ; H ; H ; None ; None ; 11.900 ns ;
; N/A ; 63.69 MHz ( period = 15.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; DiviseurDeFrequence:inst1|inst10 ; H ; H ; None ; None ; 11.700 ns ;
; N/A ; 63.69 MHz ( period = 15.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|1 ; H ; H ; None ; None ; 11.600 ns ;
; N/A ; 63.69 MHz ( period = 15.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|4 ; H ; H ; None ; None ; 11.600 ns ;
; N/A ; 63.69 MHz ( period = 15.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|5 ; H ; H ; None ; None ; 11.700 ns ;
; N/A ; 63.69 MHz ( period = 15.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|6 ; H ; H ; None ; None ; 11.700 ns ;
; N/A ; 63.69 MHz ( period = 15.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|8 ; H ; H ; None ; None ; 11.700 ns ;
; N/A ; 63.69 MHz ( period = 15.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; H ; H ; None ; None ; 11.700 ns ;
; N/A ; 63.69 MHz ( period = 15.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; H ; H ; None ; None ; 11.700 ns ;
; N/A ; 63.69 MHz ( period = 15.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; H ; H ; None ; None ; 11.700 ns ;
; N/A ; 63.69 MHz ( period = 15.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; H ; H ; None ; None ; 11.700 ns ;
; N/A ; 64.10 MHz ( period = 15.600 ns ) ; BoutonPoussoir2:inst15|inst ; CheminDeDonnees:inst|74168:inst2|49 ; H ; H ; None ; None ; 11.600 ns ;
; N/A ; 64.10 MHz ( period = 15.600 ns ) ; BoutonPoussoir2:inst15|inst ; CheminDeDonnees:inst|74168:inst2|29 ; H ; H ; None ; None ; 11.600 ns ;
; N/A ; 64.52 MHz ( period = 15.500 ns ) ; sequenceur2:inst17|inst3 ; CheminDeDonnees:inst|74168:inst2|15 ; H ; H ; None ; None ; 11.500 ns ;
; N/A ; 64.52 MHz ( period = 15.500 ns ) ; CheminDeDonnees:inst|74168:inst1|3 ; CheminDeDonnees:inst|74168:inst2|15 ; H ; H ; None ; None ; 11.500 ns ;
; N/A ; 64.52 MHz ( period = 15.500 ns ) ; CheminDeDonnees:inst|74168:inst8|49 ; CheminDeDonnees:inst|74168:inst2|15 ; H ; H ; None ; None ; 11.500 ns ;
; N/A ; 64.94 MHz ( period = 15.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; DiviseurDeFrequence:inst1|inst10 ; H ; H ; None ; None ; 11.400 ns ;
; N/A ; 64.94 MHz ( period = 15.400 ns ) ; sequenceur2:inst17|inst3 ; CheminDeDonnees:inst|74168:inst1|49 ; H ; H ; None ; None ; 11.400 ns ;
; N/A ; 64.94 MHz ( period = 15.400 ns ) ; CheminDeDonnees:inst|74168:inst1|3 ; CheminDeDonnees:inst|74168:inst1|49 ; H ; H ; None ; None ; 11.400 ns ;
; N/A ; 64.94 MHz ( period = 15.400 ns ) ; CheminDeDonnees:inst|74168:inst8|49 ; CheminDeDonnees:inst|74168:inst1|49 ; H ; H ; None ; None ; 11.400 ns ;
; N/A ; 64.94 MHz ( period = 15.400 ns ) ; sequenceur2:inst17|inst3 ; CheminDeDonnees:inst|74168:inst1|29 ; H ; H ; None ; None ; 11.400 ns ;
; N/A ; 64.94 MHz ( period = 15.400 ns ) ; CheminDeDonnees:inst|74168:inst1|3 ; CheminDeDonnees:inst|74168:inst1|29 ; H ; H ; None ; None ; 11.400 ns ;
; N/A ; 64.94 MHz ( period = 15.400 ns ) ; CheminDeDonnees:inst|74168:inst8|49 ; CheminDeDonnees:inst|74168:inst1|29 ; H ; H ; None ; None ; 11.400 ns ;
; N/A ; 64.94 MHz ( period = 15.400 ns ) ; BoutonPoussoir2:inst15|inst ; CheminDeDonnees:inst|74168:inst8|29 ; H ; H ; None ; None ; 11.400 ns ;
; N/A ; 64.94 MHz ( period = 15.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|1 ; H ; H ; None ; None ; 11.300 ns ;
; N/A ; 64.94 MHz ( period = 15.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|4 ; H ; H ; None ; None ; 11.300 ns ;
; N/A ; 64.94 MHz ( period = 15.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|5 ; H ; H ; None ; None ; 11.400 ns ;
; N/A ; 64.94 MHz ( period = 15.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|6 ; H ; H ; None ; None ; 11.400 ns ;
; N/A ; 64.94 MHz ( period = 15.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|8 ; H ; H ; None ; None ; 11.400 ns ;
; N/A ; 64.94 MHz ( period = 15.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; H ; H ; None ; None ; 11.400 ns ;
; N/A ; 64.94 MHz ( period = 15.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; H ; H ; None ; None ; 11.400 ns ;
; N/A ; 64.94 MHz ( period = 15.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; H ; H ; None ; None ; 11.400 ns ;
; N/A ; 64.94 MHz ( period = 15.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; H ; H ; None ; None ; 11.400 ns ;
; N/A ; 65.36 MHz ( period = 15.300 ns ) ; BoutonPoussoir2:inst15|inst5 ; CheminDeDonnees:inst|74168:inst2|49 ; H ; H ; None ; None ; 11.300 ns ;
; N/A ; 65.36 MHz ( period = 15.300 ns ) ; BoutonPoussoir2:inst15|inst5 ; CheminDeDonnees:inst|74168:inst2|29 ; H ; H ; None ; None ; 11.300 ns ;
; N/A ; 65.36 MHz ( period = 15.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; H ; H ; None ; None ; 11.400 ns ;
; N/A ; 65.36 MHz ( period = 15.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; H ; H ; None ; None ; 11.400 ns ;
; N/A ; 65.79 MHz ( period = 15.200 ns ) ; CheminDeDonnees:inst|74168:inst8|3 ; CheminDeDonnees:inst|74168:inst2|15 ; H ; H ; None ; None ; 11.200 ns ;
; N/A ; 66.23 MHz ( period = 15.100 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|5 ; H ; H ; None ; None ; 11.100 ns ;
; N/A ; 66.23 MHz ( period = 15.100 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|6 ; H ; H ; None ; None ; 11.100 ns ;
; N/A ; 66.23 MHz ( period = 15.100 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|8 ; H ; H ; None ; None ; 11.100 ns ;
; N/A ; 66.23 MHz ( period = 15.100 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; H ; H ; None ; None ; 11.100 ns ;
; N/A ; 66.23 MHz ( period = 15.100 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; H ; H ; None ; None ; 11.100 ns ;
; N/A ; 66.23 MHz ( period = 15.100 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; H ; H ; None ; None ; 11.100 ns ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ;
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+-----------------------------------------------------------------------------------+
; tsu ;
+-------+--------------+------------+------+-----------------------------+----------+
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
+-------+--------------+------------+------+-----------------------------+----------+
; N/A ; None ; 0.100 ns ; BP2 ; BoutonPoussoir2:inst16|inst ; H ;
; N/A ; None ; 0.000 ns ; BP1 ; BoutonPoussoir2:inst15|inst ; H ;
+-------+--------------+------------+------+-----------------------------+----------+
+-----------------------------------------------------------------------------------------------+
; tco ;
+-------+--------------+------------+-------------------------------------+--------+------------+
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
+-------+--------------+------------+-------------------------------------+--------+------------+
; N/A ; None ; 40.800 ns ; CheminDeDonnees:inst|74168:inst1|49 ; b1 ; H ;
; N/A ; None ; 40.800 ns ; CheminDeDonnees:inst|74168:inst1|49 ; a1 ; H ;
; N/A ; None ; 40.700 ns ; CheminDeDonnees:inst|74168:inst1|49 ; f1 ; H ;
; N/A ; None ; 40.700 ns ; CheminDeDonnees:inst|74168:inst1|49 ; c1 ; H ;
; N/A ; None ; 40.600 ns ; CheminDeDonnees:inst|74168:inst1|3 ; g1 ; H ;
; N/A ; None ; 40.500 ns ; CheminDeDonnees:inst|74168:inst2|29 ; G ; H ;
; N/A ; None ; 40.500 ns ; CheminDeDonnees:inst|74168:inst2|3 ; G ; H ;
; N/A ; None ; 40.500 ns ; CheminDeDonnees:inst|74168:inst2|29 ; E ; H ;
; N/A ; None ; 40.500 ns ; CheminDeDonnees:inst|74168:inst2|3 ; E ; H ;
; N/A ; None ; 40.500 ns ; CheminDeDonnees:inst|74168:inst2|29 ; D ; H ;
; N/A ; None ; 40.500 ns ; CheminDeDonnees:inst|74168:inst2|3 ; D ; H ;
; N/A ; None ; 40.500 ns ; CheminDeDonnees:inst|74168:inst2|49 ; C ; H ;
; N/A ; None ; 40.500 ns ; CheminDeDonnees:inst|74168:inst2|29 ; C ; H ;
; N/A ; None ; 40.500 ns ; CheminDeDonnees:inst|74168:inst2|49 ; B ; H ;
; N/A ; None ; 40.500 ns ; CheminDeDonnees:inst|74168:inst2|29 ; B ; H ;
; N/A ; None ; 40.500 ns ; CheminDeDonnees:inst|74168:inst2|49 ; A ; H ;
; N/A ; None ; 40.500 ns ; CheminDeDonnees:inst|74168:inst2|29 ; A ; H ;
; N/A ; None ; 40.300 ns ; CheminDeDonnees:inst|74168:inst1|3 ; d1 ; H ;
; N/A ; None ; 40.300 ns ; CheminDeDonnees:inst|74168:inst1|3 ; f1 ; H ;
; N/A ; None ; 40.300 ns ; CheminDeDonnees:inst|74168:inst1|3 ; e1 ; H ;
; N/A ; None ; 40.300 ns ; CheminDeDonnees:inst|74168:inst1|29 ; b1 ; H ;
; N/A ; None ; 40.300 ns ; CheminDeDonnees:inst|74168:inst1|29 ; a1 ; H ;
; N/A ; None ; 40.300 ns ; CheminDeDonnees:inst|74168:inst2|15 ; F ; H ;
; N/A ; None ; 40.200 ns ; CheminDeDonnees:inst|74168:inst1|29 ; d1 ; H ;
; N/A ; None ; 40.200 ns ; CheminDeDonnees:inst|74168:inst1|49 ; g1 ; H ;
; N/A ; None ; 40.200 ns ; CheminDeDonnees:inst|74168:inst1|29 ; g1 ; H ;
; N/A ; None ; 40.200 ns ; CheminDeDonnees:inst|74168:inst1|15 ; g1 ; H ;
; N/A ; None ; 40.200 ns ; CheminDeDonnees:inst|74168:inst1|29 ; e1 ; H ;
; N/A ; None ; 40.200 ns ; CheminDeDonnees:inst|74168:inst1|29 ; c1 ; H ;
; N/A ; None ; 40.200 ns ; CheminDeDonnees:inst|74168:inst2|49 ; G ; H ;
; N/A ; None ; 40.200 ns ; CheminDeDonnees:inst|74168:inst2|15 ; G ; H ;
; N/A ; None ; 40.200 ns ; CheminDeDonnees:inst|74168:inst2|3 ; C ; H ;
; N/A ; None ; 40.200 ns ; CheminDeDonnees:inst|74168:inst2|3 ; B ; H ;
; N/A ; None ; 40.200 ns ; CheminDeDonnees:inst|74168:inst2|3 ; A ; H ;
; N/A ; None ; 40.100 ns ; CheminDeDonnees:inst|74168:inst1|3 ; b1 ; H ;
; N/A ; None ; 40.100 ns ; CheminDeDonnees:inst|74168:inst1|3 ; a1 ; H ;
; N/A ; None ; 40.000 ns ; CheminDeDonnees:inst|74168:inst1|3 ; c1 ; H ;
; N/A ; None ; 39.900 ns ; CheminDeDonnees:inst|74168:inst1|29 ; f1 ; H ;
; N/A ; None ; 39.100 ns ; BoutonPoussoir2:inst15|inst ; BP1out ; H ;
; N/A ; None ; 38.800 ns ; BoutonPoussoir2:inst15|inst5 ; BP1out ; H ;
; N/A ; None ; 38.000 ns ; CheminDeDonnees:inst|74168:inst2|15 ; C ; H ;
; N/A ; None ; 38.000 ns ; CheminDeDonnees:inst|74168:inst2|15 ; B ; H ;
; N/A ; None ; 38.000 ns ; CheminDeDonnees:inst|74168:inst2|15 ; A ; H ;
; N/A ; None ; 37.900 ns ; CheminDeDonnees:inst|74168:inst1|15 ; b1 ; H ;
; N/A ; None ; 37.900 ns ; CheminDeDonnees:inst|74168:inst1|15 ; a1 ; H ;
; N/A ; None ; 37.900 ns ; CheminDeDonnees:inst|74168:inst2|49 ; F ; H ;
; N/A ; None ; 37.900 ns ; CheminDeDonnees:inst|74168:inst2|3 ; F ; H ;
; N/A ; None ; 37.800 ns ; CheminDeDonnees:inst|74168:inst1|15 ; f1 ; H ;
; N/A ; None ; 37.800 ns ; CheminDeDonnees:inst|74168:inst1|15 ; c1 ; H ;
; N/A ; None ; 37.700 ns ; CheminDeDonnees:inst|74168:inst2|15 ; E ; H ;
; N/A ; None ; 37.700 ns ; CheminDeDonnees:inst|74168:inst2|15 ; D ; H ;
; N/A ; None ; 37.600 ns ; CheminDeDonnees:inst|74168:inst2|29 ; F ; H ;
; N/A ; None ; 37.500 ns ; CheminDeDonnees:inst|74168:inst1|15 ; d1 ; H ;
; N/A ; None ; 37.500 ns ; CheminDeDonnees:inst|74168:inst1|15 ; e1 ; H ;
; N/A ; None ; 36.100 ns ; BoutonPoussoir2:inst15|inst ; Reset ; H ;
; N/A ; None ; 35.800 ns ; BoutonPoussoir2:inst15|inst5 ; Reset ; H ;
; N/A ; None ; 31.900 ns ; sequenceur2:inst17|inst3 ; Count ; H ;
+-------+--------------+------------+-------------------------------------+--------+------------+
+-----------------------------------------------------------------------------------------+
; th ;
+---------------+-------------+-----------+------+-----------------------------+----------+
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
+---------------+-------------+-----------+------+-----------------------------+----------+
; N/A ; None ; 5.700 ns ; BP1 ; BoutonPoussoir2:inst15|inst ; H ;
; N/A ; None ; 5.600 ns ; BP2 ; BoutonPoussoir2:inst16|inst ; H ;
+---------------+-------------+-----------+------+-----------------------------+----------+
+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Info: Processing started: Wed Jan 24 17:22:09 2018
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Chronometre -c Chronometre
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
Info: Assuming node "H" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
Info: Detected ripple clock "DiviseurDeFrequence:inst1|7456:inst7|5" as buffer
Info: Detected ripple clock "DiviseurDeFrequence:inst1|inst10" as buffer
Info: Clock "H" has Internal fmax of 42.02 MHz between source register "DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8" and destination register "DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2" (period= 23.8 ns)
Info: + Longest register to register delay is 19.700 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_H27; Fanout = 2; REG Node = 'DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8'
Info: 2: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = LC5_H27; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1|8count:inst|f8count:sub|245'
Info: 3: + IC(0.000 ns) + CELL(0.300 ns) = 1.800 ns; Loc. = LC6_H27; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1|8count:inst|f8count:sub|246'
Info: 4: + IC(0.000 ns) + CELL(0.300 ns) = 2.100 ns; Loc. = LC7_H27; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1|8count:inst|f8count:sub|247'
Info: 5: + IC(0.000 ns) + CELL(0.300 ns) = 2.400 ns; Loc. = LC8_H27; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1|8count:inst|f8count:sub|248'
Info: 6: + IC(1.100 ns) + CELL(0.300 ns) = 3.800 ns; Loc. = LC1_H29; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1|8count:inst|f8count:sub|249'
Info: 7: + IC(0.000 ns) + CELL(0.300 ns) = 4.100 ns; Loc. = LC2_H29; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1|8count:inst|f8count:sub|250'
Info: 8: + IC(0.000 ns) + CELL(0.300 ns) = 4.400 ns; Loc. = LC3_H29; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1|8count:inst|f8count:sub|251'
Info: 9: + IC(0.000 ns) + CELL(0.300 ns) = 4.700 ns; Loc. = LC4_H29; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1|8count:inst|f8count:sub|302'
Info: 10: + IC(0.000 ns) + CELL(0.300 ns) = 5.000 ns; Loc. = LC5_H29; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|245'
Info: 11: + IC(0.000 ns) + CELL(0.300 ns) = 5.300 ns; Loc. = LC6_H29; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|246'
Info: 12: + IC(0.000 ns) + CELL(0.300 ns) = 5.600 ns; Loc. = LC7_H29; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|247'
Info: 13: + IC(0.000 ns) + CELL(0.300 ns) = 5.900 ns; Loc. = LC8_H29; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|248'
Info: 14: + IC(1.100 ns) + CELL(0.300 ns) = 7.300 ns; Loc. = LC1_H31; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|249'
Info: 15: + IC(0.000 ns) + CELL(0.300 ns) = 7.600 ns; Loc. = LC2_H31; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|250'
Info: 16: + IC(0.000 ns) + CELL(0.300 ns) = 7.900 ns; Loc. = LC3_H31; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|251'
Info: 17: + IC(0.000 ns) + CELL(0.300 ns) = 8.200 ns; Loc. = LC4_H31; Fanout = 1; COMB Node = 'DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|302'
Info: 18: + IC(0.000 ns) + CELL(1.200 ns) = 9.400 ns; Loc. = LC5_H31; Fanout = 11; COMB Node = 'DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|302~5'
Info: 19: + IC(2.900 ns) + CELL(2.400 ns) = 14.700 ns; Loc. = LC3_H27; Fanout = 7; COMB Node = 'DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|302~5_wirecell'
Info: 20: + IC(3.000 ns) + CELL(2.000 ns) = 19.700 ns; Loc. = LC3_H31; Fanout = 2; REG Node = 'DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2'
Info: Total cell delay = 11.600 ns ( 58.88 % )
Info: Total interconnect delay = 8.100 ns ( 41.12 % )
Info: - Smallest clock skew is -0.100 ns
Info: + Shortest clock path from clock "H" to destination register is 11.800 ns
Info: 1: + IC(0.000 ns) + CELL(2.900 ns) = 2.900 ns; Loc. = PIN_91; Fanout = 3; CLK Node = 'H'
Info: 2: + IC(4.100 ns) + CELL(1.400 ns) = 8.400 ns; Loc. = LC1_H41; Fanout = 18; REG Node = 'DiviseurDeFrequence:inst1|7456:inst7|5'
Info: 3: + IC(3.400 ns) + CELL(0.000 ns) = 11.800 ns; Loc. = LC3_H31; Fanout = 2; REG Node = 'DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2'
Info: Total cell delay = 4.300 ns ( 36.44 % )
Info: Total interconnect delay = 7.500 ns ( 63.56 % )
Info: - Longest clock path from clock "H" to source register is 11.900 ns
Info: 1: + IC(0.000 ns) + CELL(2.900 ns) = 2.900 ns; Loc. = PIN_91; Fanout = 3; CLK Node = 'H'
Info: 2: + IC(4.100 ns) + CELL(1.400 ns) = 8.400 ns; Loc. = LC1_H41; Fanout = 18; REG Node = 'DiviseurDeFrequence:inst1|7456:inst7|5'
Info: 3: + IC(3.500 ns) + CELL(0.000 ns) = 11.900 ns; Loc. = LC5_H27; Fanout = 2; REG Node = 'DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8'
Info: Total cell delay = 4.300 ns ( 36.13 % )
Info: Total interconnect delay = 7.600 ns ( 63.87 % )
Info: + Micro clock to output delay of source is 1.400 ns
Info: + Micro setup delay of destination is 2.600 ns
Info: tsu for register "BoutonPoussoir2:inst16|inst" (data pin = "BP2", clock pin = "H") is 0.100 ns
Info: + Longest pin to register delay is 20.200 ns
Info: 1: + IC(0.000 ns) + CELL(10.300 ns) = 10.300 ns; Loc. = PIN_29; Fanout = 1; PIN Node = 'BP2'
Info: 2: + IC(8.200 ns) + CELL(1.700 ns) = 20.200 ns; Loc. = LC1_H32; Fanout = 2; REG Node = 'BoutonPoussoir2:inst16|inst'
Info: Total cell delay = 12.000 ns ( 59.41 % )
Info: Total interconnect delay = 8.200 ns ( 40.59 % )
Info: + Micro setup delay of destination is 2.600 ns
Info: - Shortest clock path from clock "H" to destination register is 22.700 ns
Info: 1: + IC(0.000 ns) + CELL(2.900 ns) = 2.900 ns; Loc. = PIN_91; Fanout = 3; CLK Node = 'H'
Info: 2: + IC(4.100 ns) + CELL(1.400 ns) = 8.400 ns; Loc. = LC1_H41; Fanout = 18; REG Node = 'DiviseurDeFrequence:inst1|7456:inst7|5'
Info: 3: + IC(3.500 ns) + CELL(1.400 ns) = 13.300 ns; Loc. = LC1_H27; Fanout = 18; REG Node = 'DiviseurDeFrequence:inst1|inst10'
Info: 4: + IC(9.400 ns) + CELL(0.000 ns) = 22.700 ns; Loc. = LC1_H32; Fanout = 2; REG Node = 'BoutonPoussoir2:inst16|inst'
Info: Total cell delay = 5.700 ns ( 25.11 % )
Info: Total interconnect delay = 17.000 ns ( 74.89 % )
Info: tco from clock "H" to destination pin "b1" through register "CheminDeDonnees:inst|74168:inst1|49" is 40.800 ns
Info: + Longest clock path from clock "H" to source register is 22.700 ns
Info: 1: + IC(0.000 ns) + CELL(2.900 ns) = 2.900 ns; Loc. = PIN_91; Fanout = 3; CLK Node = 'H'
Info: 2: + IC(4.100 ns) + CELL(1.400 ns) = 8.400 ns; Loc. = LC1_H41; Fanout = 18; REG Node = 'DiviseurDeFrequence:inst1|7456:inst7|5'
Info: 3: + IC(3.500 ns) + CELL(1.400 ns) = 13.300 ns; Loc. = LC1_H27; Fanout = 18; REG Node = 'DiviseurDeFrequence:inst1|inst10'
Info: 4: + IC(9.400 ns) + CELL(0.000 ns) = 22.700 ns; Loc. = LC1_H33; Fanout = 11; REG Node = 'CheminDeDonnees:inst|74168:inst1|49'
Info: Total cell delay = 5.700 ns ( 25.11 % )
Info: Total interconnect delay = 17.000 ns ( 74.89 % )
Info: + Micro clock to output delay of source is 1.400 ns
Info: + Longest register to pin delay is 16.700 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_H33; Fanout = 11; REG Node = 'CheminDeDonnees:inst|74168:inst1|49'
Info: 2: + IC(3.400 ns) + CELL(2.700 ns) = 6.100 ns; Loc. = LC8_H35; Fanout = 1; COMB Node = 'CheminDeDonnees:inst|7446:inst4|97~0'
Info: 3: + IC(5.600 ns) + CELL(5.000 ns) = 16.700 ns; Loc. = PIN_18; Fanout = 0; PIN Node = 'b1'
Info: Total cell delay = 7.700 ns ( 46.11 % )
Info: Total interconnect delay = 9.000 ns ( 53.89 % )
Info: th for register "BoutonPoussoir2:inst15|inst" (data pin = "BP1", clock pin = "H") is 5.700 ns
Info: + Longest clock path from clock "H" to destination register is 22.700 ns
Info: 1: + IC(0.000 ns) + CELL(2.900 ns) = 2.900 ns; Loc. = PIN_91; Fanout = 3; CLK Node = 'H'
Info: 2: + IC(4.100 ns) + CELL(1.400 ns) = 8.400 ns; Loc. = LC1_H41; Fanout = 18; REG Node = 'DiviseurDeFrequence:inst1|7456:inst7|5'
Info: 3: + IC(3.500 ns) + CELL(1.400 ns) = 13.300 ns; Loc. = LC1_H27; Fanout = 18; REG Node = 'DiviseurDeFrequence:inst1|inst10'
Info: 4: + IC(9.400 ns) + CELL(0.000 ns) = 22.700 ns; Loc. = LC1_H39; Fanout = 9; REG Node = 'BoutonPoussoir2:inst15|inst'
Info: Total cell delay = 5.700 ns ( 25.11 % )
Info: Total interconnect delay = 17.000 ns ( 74.89 % )
Info: + Micro hold delay of destination is 3.100 ns
Info: - Shortest pin to register delay is 20.100 ns
Info: 1: + IC(0.000 ns) + CELL(10.300 ns) = 10.300 ns; Loc. = PIN_28; Fanout = 1; PIN Node = 'BP1'
Info: 2: + IC(8.100 ns) + CELL(1.700 ns) = 20.100 ns; Loc. = LC1_H39; Fanout = 9; REG Node = 'BoutonPoussoir2:inst15|inst'
Info: Total cell delay = 12.000 ns ( 59.70 % )
Info: Total interconnect delay = 8.100 ns ( 40.30 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
Info: Peak virtual memory: 156 megabytes
Info: Processing ended: Wed Jan 24 17:22:10 2018
Info: Elapsed time: 00:00:01
Info: Total CPU time (on all processors): 00:00:01

56
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--------------------------------------------------------------------------------------
Timing Analyzer Summary
--------------------------------------------------------------------------------------
Type : Worst-case tsu
Slack : N/A
Required Time : None
Actual Time : 0.100 ns
From : BP2
To : BoutonPoussoir2:inst16|inst
From Clock : --
To Clock : H
Failed Paths : 0
Type : Worst-case tco
Slack : N/A
Required Time : None
Actual Time : 40.800 ns
From : CheminDeDonnees:inst|74168:inst1|49
To : a1
From Clock : H
To Clock : --
Failed Paths : 0
Type : Worst-case th
Slack : N/A
Required Time : None
Actual Time : 5.700 ns
From : BP1
To : BoutonPoussoir2:inst15|inst
From Clock : --
To Clock : H
Failed Paths : 0
Type : Clock Setup: 'H'
Slack : N/A
Required Time : None
Actual Time : 42.02 MHz ( period = 23.800 ns )
From : DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8
To : DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3
From Clock : H
To Clock : H
Failed Paths : 0
Type : Total number of failed paths
Slack :
Required Time :
Actual Time :
From :
To :
From Clock :
To Clock :
Failed Paths : 0
--------------------------------------------------------------------------------------

374
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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818
SLEA/DiviseurDeFrequence.bdf Normal file
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@ -0,0 +1,818 @@
/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
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(text "GND" (rect 400 256 424 268)(font "Arial" ))
(pt 392 272)
(pt 440 272)
)
(connector
(text "VCC" (rect 400 336 423 348)(font "Arial" ))
(pt 392 352)
(pt 440 352)
)
(connector
(text "VCC" (rect 400 320 423 332)(font "Arial" ))
(pt 392 336)
(pt 440 336)
)
(connector
(text "DIV5" (rect 360 352 384 364)(font "Arial" ))
(pt 344 368)
(pt 440 368)
)
(connector
(text "GND" (rect 680 176 704 188)(font "Arial" ))
(pt 672 192)
(pt 728 192)
)
(connector
(text "VCC" (rect 680 160 703 172)(font "Arial" ))
(pt 672 176)
(pt 728 176)
)
(connector
(text "VCC" (rect 680 192 703 204)(font "Arial" ))
(pt 672 208)
(pt 728 208)
)
(connector
(text "VCC" (rect 680 224 703 236)(font "Arial" ))
(pt 672 240)
(pt 728 240)
)
(connector
(text "GND" (rect 680 240 704 252)(font "Arial" ))
(pt 672 256)
(pt 728 256)
)
(connector
(pt 624 304)
(pt 728 304)
)
(connector
(text "VCC" (rect 680 272 703 284)(font "Arial" ))
(pt 672 288)
(pt 728 288)
)
(connector
(text "GND" (rect 680 256 704 268)(font "Arial" ))
(pt 672 272)
(pt 728 272)
)
(connector
(text "VCC" (rect 686 336 709 348)(font "Arial" ))
(pt 672 352)
(pt 728 352)
)
(connector
(text "VCC" (rect 680 320 703 332)(font "Arial" ))
(pt 672 336)
(pt 728 336)
)
(connector
(text "DIV5" (rect 640 352 664 364)(font "Arial" ))
(pt 632 368)
(pt 728 368)
)
(connector
(text "DIV5" (rect 1176 360 1200 372)(font "Arial" ))
(pt 1160 352)
(pt 1216 352)
)
(connector
(text "VCC" (rect 680 208 703 220)(font "Arial" ))
(pt 672 224)
(pt 728 224)
)
(connector
(text "GND" (rect 400 224 424 236)(font "Arial" ))
(pt 392 240)
(pt 440 240)
)
(connector
(pt 944 304)
(pt 944 264)
)
(connector
(pt 944 120)
(pt 944 216)
)
(connector
(pt 1208 336)
(pt 1208 304)
)
(connector
(pt 1216 336)
(pt 1208 336)
)
(connector
(text "GND" (rect 400 304 424 316)(font "Arial" ))
(pt 392 320)
(pt 440 320)
)
(connector
(text "GND" (rect 680 304 704 316)(font "Arial" ))
(pt 672 320)
(pt 728 320)
)
(connector
(pt 424 120)
(pt 712 120)
)
(connector
(pt 712 120)
(pt 944 120)
)
(connector
(pt 848 304)
(pt 944 304)
)
(connector
(pt 944 304)
(pt 1208 304)
)
(connector
(text "DIV5" (rect 301 432 325 444)(font "Arial" ))
(pt 288 448)
(pt 344 448)
)
(connector
(text "H" (rect 120 448 128 460)(font "Arial" ))
(pt 112 464)
(pt 184 464)
)
(junction (pt 712 120))
(junction (pt 944 304))

43
SLEA/DiviseurDeFrequence.bsf Normal file
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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
(header "symbol" (version "1.1"))
(symbol
(rect 16 16 112 112)
(text "DiviseurDeFrequence" (rect 5 0 127 14)(font "Arial" (font_size 8)))
(text "inst" (rect 8 80 25 92)(font "Arial" ))
(port
(pt 0 32)
(input)
(text "H" (rect 0 0 8 14)(font "Arial" (font_size 8)))
(text "H" (rect 21 27 29 41)(font "Arial" (font_size 8)))
(line (pt 0 32)(pt 16 32)(line_width 1))
)
(port
(pt 96 32)
(output)
(text "100Hz" (rect 0 0 36 14)(font "Arial" (font_size 8)))
(text "100Hz" (rect 39 27 75 41)(font "Arial" (font_size 8)))
(line (pt 96 32)(pt 80 32)(line_width 1))
)
(drawing
(rectangle (rect 16 16 80 80)(line_width 1))
)
)

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library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
ENTITY Sequenceur_vhdl is
port(
H, BP1, BP2: in std_logic;
Count, Reset: out std_logic
);
END;
ARCHITECTURE Sequenceur_vhdl of Sequenceur_vhdl is
BEGIN
PROCESS(H)

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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Assembler Quartus II " "Info: Running Quartus II Assembler" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jan 24 17:22:06 2018 " "Info: Processing started: Wed Jan 24 17:22:06 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_asm --read_settings_files=off --write_settings_files=off Chronometre -c Chronometre " "Info: Command: quartus_asm --read_settings_files=off --write_settings_files=off Chronometre -c Chronometre" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IASM_ASM_GENERATING_PROGRAMMING_FILES" "" "Info: Assembler is generating device programming files" { } { } 0 0 "Assembler is generating device programming files" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Assembler 0 s 0 s Quartus II " "Info: Quartus II Assembler was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "176 " "Info: Peak virtual memory: 176 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jan 24 17:22:08 2018 " "Info: Processing ended: Wed Jan 24 17:22:08 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}

5
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<?xml version="1.0" ?>
<LOG_ROOT>
<PROJECT NAME="Chronometre">
</PROJECT>
</LOG_ROOT>

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v1

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Quartus_Version = Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
Version_Index = 167832322
Creation_Time = Fri Dec 08 13:44:11 2017

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27

16
SLEA/db/Chronometre.fit.qmsg Normal file
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jan 24 17:22:00 2018 " "Info: Processing started: Wed Jan 24 17:22:00 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off Chronometre -c Chronometre " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off Chronometre -c Chronometre" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IMPP_MPP_USER_DEVICE" "Chronometre EPF10K70RC240-4 " "Info: Selected device EPF10K70RC240-4 for design \"Chronometre\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
{ "Warning" "WCPT_FEATURE_DISABLED_POST" "SignalProbe " "Warning: Feature SignalProbe is not available with your current license" { } { } 0 0 "Feature %1!s! is not available with your current license" 0 0 "" 0 -1}
{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
{ "Info" "ITAN_TDC_DEFAULT_OPTIMIZATION_GOALS" "" "Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" { { "Info" "ITAN_TDC_ASSUMED_DEFAULT_REQUIREMENT" "fmax 1000 MHz " "Info: Assuming a global fmax requirement of 1000 MHz" { } { } 0 0 "Assuming a global %1!s! requirement of %2!s!" 0 0 "" 0 -1} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tsu " "Info: Not setting a global tsu requirement" { } { } 0 0 "Not setting a global %1!s! requirement" 0 0 "" 0 -1} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tco " "Info: Not setting a global tco requirement" { } { } 0 0 "Not setting a global %1!s! requirement" 0 0 "" 0 -1} { "Info" "ITAN_TDC_NO_DEFAULT_REQUIREMENT" "tpd " "Info: Not setting a global tpd requirement" { } { } 0 0 "Not setting a global %1!s! requirement" 0 0 "" 0 -1} } { } 0 0 "Timing requirements not specified -- optimizing circuit to achieve the following default global requirements" 0 0 "" 0 -1}
{ "Info" "IF10KE_F10KE_WIRE_LUT_INSERTED" "1 " "Info: Inserted 1 logic cells in first fitting attempt" { } { } 0 0 "Inserted %1!d! logic cells in first fitting attempt" 0 0 "" 0 -1}
{ "Info" "IFIT_FIT_ATTEMPT" "1 Wed Jan 24 2018 17:22:01 " "Info: Started fitting attempt 1 on Wed Jan 24 2018 at 17:22:01" { } { } 0 0 "Started fitting attempt %1!d! on %2!s! at %3!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 1 Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "194 " "Info: Peak virtual memory: 194 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jan 24 17:22:05 2018 " "Info: Processing ended: Wed Jan 24 17:22:05 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:04 " "Info: Total CPU time (on all processors): 00:00:04" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}

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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Functional Simulation Netlist Generation Quartus II " "Info: Running Quartus II Functional Simulation Netlist Generation" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jan 24 16:27:47 2018 " "Info: Processing started: Wed Jan 24 16:27:47 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Chronometre -c Chronometre --generate_functional_sim_netlist " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Chronometre -c Chronometre --generate_functional_sim_netlist" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Decodeur.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file Decodeur.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Decodeur " "Info: Found entity 1: Decodeur" { } { { "Decodeur.bdf" "" { Schematic "U:/SLEA/Decodeur.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "BoutonPoussoir.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file BoutonPoussoir.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 BoutonPoussoir " "Info: Found entity 1: BoutonPoussoir" { } { { "BoutonPoussoir.bdf" "" { Schematic "U:/SLEA/BoutonPoussoir.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "BoutonPoussoir2.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file BoutonPoussoir2.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 BoutonPoussoir2 " "Info: Found entity 1: BoutonPoussoir2" { } { { "BoutonPoussoir2.bdf" "" { Schematic "U:/SLEA/BoutonPoussoir2.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DiviseurDeFrequence.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file DiviseurDeFrequence.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 DiviseurDeFrequence " "Info: Found entity 1: DiviseurDeFrequence" { } { { "DiviseurDeFrequence.bdf" "" { Schematic "U:/SLEA/DiviseurDeFrequence.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CheminDeDonnees.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file CheminDeDonnees.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 CheminDeDonnees " "Info: Found entity 1: CheminDeDonnees" { } { { "CheminDeDonnees.bdf" "" { Schematic "U:/SLEA/CheminDeDonnees.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Sequenceur.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file Sequenceur.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Sequenceur " "Info: Found entity 1: Sequenceur" { } { { "Sequenceur.bdf" "" { Schematic "U:/SLEA/Sequenceur.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CHRONO.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file CHRONO.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 CHRONO " "Info: Found entity 1: CHRONO" { } { { "CHRONO.bdf" "" { Schematic "U:/SLEA/CHRONO.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sequenceur2.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file sequenceur2.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 sequenceur2 " "Info: Found entity 1: sequenceur2" { } { { "sequenceur2.bdf" "" { Schematic "U:/SLEA/sequenceur2.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "sequenceur2 " "Info: Elaborating entity \"sequenceur2\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Functional Simulation Netlist Generation 0 s 0 s Quartus II " "Info: Quartus II Functional Simulation Netlist Generation was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "190 " "Info: Peak virtual memory: 190 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jan 24 16:27:48 2018 " "Info: Processing ended: Wed Jan 24 16:27:48 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}

471
SLEA/db/Chronometre.hier_info Normal file
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@ -0,0 +1,471 @@
|CHRONO
A <= CheminDeDonnees:inst.A
H => DiviseurDeFrequence:inst1.H
Count <= sequenceur2:inst17.COUNT
BP1 => BoutonPoussoir2:inst15.BP
BP2 => BoutonPoussoir2:inst16.BP
Reset <= sequenceur2:inst17.RESET
B <= CheminDeDonnees:inst.B
C <= CheminDeDonnees:inst.C
D <= CheminDeDonnees:inst.D
E <= CheminDeDonnees:inst.E
F <= CheminDeDonnees:inst.F
G <= CheminDeDonnees:inst.G
a1 <= CheminDeDonnees:inst.a1
b1 <= CheminDeDonnees:inst.b1
c1 <= CheminDeDonnees:inst.c1
e1 <= CheminDeDonnees:inst.e1
f1 <= CheminDeDonnees:inst.f1
g1 <= CheminDeDonnees:inst.g1
d1 <= CheminDeDonnees:inst.d1
pointSeconde <= <VCC>
pointDixieme <= <GND>
BP1out <= BP1a.DB_MAX_OUTPUT_PORT_TYPE
|CHRONO|CheminDeDonnees:inst
A <= 7446:inst7.OA
COUNT => 74168:inst8.ENPN
COUNT => 74168:inst8.ENTN
H => 74168:inst8.CLK
H => 74168:inst1.CLK
H => 74168:inst2.CLK
RESET => 74168:inst8.LDN
RESET => 74168:inst1.LDN
RESET => 74168:inst2.LDN
B <= 7446:inst7.OB
C <= 7446:inst7.OC
D <= 7446:inst7.OD
E <= 7446:inst7.OE
F <= 7446:inst7.OF
G <= 7446:inst7.OG
a1 <= 7446:inst4.OA
b1 <= 7446:inst4.OB
c1 <= 7446:inst4.OC
e1 <= 7446:inst4.OE
f1 <= 7446:inst4.OF
g1 <= 7446:inst4.OG
d1 <= 7446:inst4.OD
pointSeconde <= <VCC>
pointDixieme <= <GND>
|CHRONO|CheminDeDonnees:inst|7446:inst7
OA <= 96.DB_MAX_OUTPUT_PORT_TYPE
B => 27.IN0
LTN => 27.IN1
LTN => 25.IN1
LTN => 29.IN1
LTN => 13.IN5
LTN => 38.IN3
BIN => 37.IN0
C => 25.IN0
D => 14.IN0
A => 29.IN0
RBIN => 15.IN0
OB <= 97.DB_MAX_OUTPUT_PORT_TYPE
OC <= 98.DB_MAX_OUTPUT_PORT_TYPE
OD <= 99.DB_MAX_OUTPUT_PORT_TYPE
RBON <= 13.DB_MAX_OUTPUT_PORT_TYPE
OE <= 100.DB_MAX_OUTPUT_PORT_TYPE
OF <= 101.DB_MAX_OUTPUT_PORT_TYPE
OG <= 102.DB_MAX_OUTPUT_PORT_TYPE
|CHRONO|CheminDeDonnees:inst|74168:inst2
Q0 <= 3.DB_MAX_OUTPUT_PORT_TYPE
CLK => 3.CLK
CLK => 15.CLK
CLK => 49.CLK
CLK => 29.CLK
D0 => 6.IN0
LDN => 71.IN0
LDN => 8.IN1
LDN => 27.IN1
LDN => 50.IN1
LDN => 11.IN1
ENTN => 66.IN0
ENTN => 114.IN0
ENPN => 66.IN1
Q1 <= 15.DB_MAX_OUTPUT_PORT_TYPE
D1 => 13.IN0
D3 => 72.IN0
U/DN => 101.IN0
U/DN => 93.IN0
U/DN => 97.IN0
U/DN => 67.IN0
U/DN => 102.IN4
U/DN => 102.IN5
U/DN => 86.IN1
U/DN => 87.IN2
U/DN => 77.IN0
D2 => 28.IN0
Q2 <= 29.DB_MAX_OUTPUT_PORT_TYPE
Q3 <= 49.DB_MAX_OUTPUT_PORT_TYPE
TCN <= 79.DB_MAX_OUTPUT_PORT_TYPE
|CHRONO|CheminDeDonnees:inst|74168:inst1
Q0 <= 3.DB_MAX_OUTPUT_PORT_TYPE
CLK => 3.CLK
CLK => 15.CLK
CLK => 49.CLK
CLK => 29.CLK
D0 => 6.IN0
LDN => 71.IN0
LDN => 8.IN1
LDN => 27.IN1
LDN => 50.IN1
LDN => 11.IN1
ENTN => 66.IN0
ENTN => 114.IN0
ENPN => 66.IN1
Q1 <= 15.DB_MAX_OUTPUT_PORT_TYPE
D1 => 13.IN0
D3 => 72.IN0
U/DN => 101.IN0
U/DN => 93.IN0
U/DN => 97.IN0
U/DN => 67.IN0
U/DN => 102.IN4
U/DN => 102.IN5
U/DN => 86.IN1
U/DN => 87.IN2
U/DN => 77.IN0
D2 => 28.IN0
Q2 <= 29.DB_MAX_OUTPUT_PORT_TYPE
Q3 <= 49.DB_MAX_OUTPUT_PORT_TYPE
TCN <= 79.DB_MAX_OUTPUT_PORT_TYPE
|CHRONO|CheminDeDonnees:inst|74168:inst8
Q0 <= 3.DB_MAX_OUTPUT_PORT_TYPE
CLK => 3.CLK
CLK => 15.CLK
CLK => 49.CLK
CLK => 29.CLK
D0 => 6.IN0
LDN => 71.IN0
LDN => 8.IN1
LDN => 27.IN1
LDN => 50.IN1
LDN => 11.IN1
ENTN => 66.IN0
ENTN => 114.IN0
ENPN => 66.IN1
Q1 <= 15.DB_MAX_OUTPUT_PORT_TYPE
D1 => 13.IN0
D3 => 72.IN0
U/DN => 101.IN0
U/DN => 93.IN0
U/DN => 97.IN0
U/DN => 67.IN0
U/DN => 102.IN4
U/DN => 102.IN5
U/DN => 86.IN1
U/DN => 87.IN2
U/DN => 77.IN0
D2 => 28.IN0
Q2 <= 29.DB_MAX_OUTPUT_PORT_TYPE
Q3 <= 49.DB_MAX_OUTPUT_PORT_TYPE
TCN <= 79.DB_MAX_OUTPUT_PORT_TYPE
|CHRONO|CheminDeDonnees:inst|7446:inst4
OA <= 96.DB_MAX_OUTPUT_PORT_TYPE
B => 27.IN0
LTN => 27.IN1
LTN => 25.IN1
LTN => 29.IN1
LTN => 13.IN5
LTN => 38.IN3
BIN => 37.IN0
C => 25.IN0
D => 14.IN0
A => 29.IN0
RBIN => 15.IN0
OB <= 97.DB_MAX_OUTPUT_PORT_TYPE
OC <= 98.DB_MAX_OUTPUT_PORT_TYPE
OD <= 99.DB_MAX_OUTPUT_PORT_TYPE
RBON <= 13.DB_MAX_OUTPUT_PORT_TYPE
OE <= 100.DB_MAX_OUTPUT_PORT_TYPE
OF <= 101.DB_MAX_OUTPUT_PORT_TYPE
OG <= 102.DB_MAX_OUTPUT_PORT_TYPE
|CHRONO|DiviseurDeFrequence:inst1
100Hz <= inst10.DB_MAX_OUTPUT_PORT_TYPE
H => 7456:inst7.CLKA
|CHRONO|DiviseurDeFrequence:inst1|8count:inst4
clk => f8count:sub.clk
clrn => f8count:sub.clrn
setn => f8count:sub.setn
ldn => f8count:sub.ldn
dnup => f8count:sub.dnup
gn => f8count:sub.gn
h => f8count:sub.h
g => f8count:sub.g
f => f8count:sub.f
e => f8count:sub.e
d => f8count:sub.d
c => f8count:sub.c
b => f8count:sub.b
a => f8count:sub.a
qh <= f8count:sub.qh
qg <= f8count:sub.qg
qf <= f8count:sub.qf
qe <= f8count:sub.qe
qd <= f8count:sub.qd
qc <= f8count:sub.qc
qb <= f8count:sub.qb
qa <= f8count:sub.qa
cout <= f8count:sub.cout
|CHRONO|DiviseurDeFrequence:inst1|8count:inst4|f8count:sub
COUT <= 302.DB_MAX_OUTPUT_PORT_TYPE
DNUP => 242.IN0
DNUP => 236.IN0
DNUP => 230.IN0
DNUP => 224.IN0
DNUP => 218.IN0
DNUP => 212.IN0
DNUP => 206.IN0
DNUP => 200.IN0
DNUP => 286.IN0
DNUP => 288.IN0
DNUP => 290.IN0
DNUP => 292.IN0
DNUP => 294.IN0
DNUP => 296.IN0
DNUP => 298.IN0
DNUP => 300.IN0
GN => 301.DATAIN
A => 255.IN0
A => 164.IN1
A => 195.IN0
SETN => 255.IN1
SETN => 253.IN1
SETN => 259.IN1
SETN => 257.IN1
SETN => 263.IN1
SETN => 261.IN1
SETN => 267.IN1
SETN => 265.IN1
SETN => 271.IN1
SETN => 269.IN1
SETN => 275.IN1
SETN => 273.IN1
SETN => 279.IN1
SETN => 277.IN1
SETN => 283.IN1
SETN => 281.IN1
CLRN => 165.IN1
CLRN => 169.IN1
CLRN => 173.IN1
CLRN => 177.IN1
CLRN => 181.IN1
CLRN => 185.IN1
CLRN => 189.IN1
CLRN => 193.IN1
CLK => 8.CLK
CLK => 7.CLK
CLK => 6.CLK
CLK => 5.CLK
CLK => 4.CLK
CLK => 3.CLK
CLK => 2.CLK
CLK => 1.CLK
LDN => 197.IN0
LDN => 205.IN0
LDN => 211.IN0
LDN => 217.IN0
LDN => 223.IN0
LDN => 228.IN0
LDN => 234.IN0
LDN => 241.IN0
B => 259.IN0
B => 168.IN1
B => 202.IN0
C => 263.IN0
C => 172.IN1
C => 208.IN0
D => 267.IN0
D => 176.IN1
D => 214.IN0
E => 271.IN0
E => 180.IN1
E => 220.IN0
F => 275.IN0
F => 184.IN1
F => 226.IN0
G => 279.IN0
G => 188.IN1
G => 232.IN0
H => 283.IN0
H => 192.IN1
H => 238.IN0
QH <= 1.DB_MAX_OUTPUT_PORT_TYPE
QG <= 2.DB_MAX_OUTPUT_PORT_TYPE
QF <= 3.DB_MAX_OUTPUT_PORT_TYPE
QE <= 4.DB_MAX_OUTPUT_PORT_TYPE
QD <= 5.DB_MAX_OUTPUT_PORT_TYPE
QC <= 6.DB_MAX_OUTPUT_PORT_TYPE
QB <= 7.DB_MAX_OUTPUT_PORT_TYPE
QA <= 8.DB_MAX_OUTPUT_PORT_TYPE
|CHRONO|DiviseurDeFrequence:inst1|8count:inst
clk => f8count:sub.clk
clrn => f8count:sub.clrn
setn => f8count:sub.setn
ldn => f8count:sub.ldn
dnup => f8count:sub.dnup
gn => f8count:sub.gn
h => f8count:sub.h
g => f8count:sub.g
f => f8count:sub.f
e => f8count:sub.e
d => f8count:sub.d
c => f8count:sub.c
b => f8count:sub.b
a => f8count:sub.a
qh <= f8count:sub.qh
qg <= f8count:sub.qg
qf <= f8count:sub.qf
qe <= f8count:sub.qe
qd <= f8count:sub.qd
qc <= f8count:sub.qc
qb <= f8count:sub.qb
qa <= f8count:sub.qa
cout <= f8count:sub.cout
|CHRONO|DiviseurDeFrequence:inst1|8count:inst|f8count:sub
COUT <= 302.DB_MAX_OUTPUT_PORT_TYPE
DNUP => 242.IN0
DNUP => 236.IN0
DNUP => 230.IN0
DNUP => 224.IN0
DNUP => 218.IN0
DNUP => 212.IN0
DNUP => 206.IN0
DNUP => 200.IN0
DNUP => 286.IN0
DNUP => 288.IN0
DNUP => 290.IN0
DNUP => 292.IN0
DNUP => 294.IN0
DNUP => 296.IN0
DNUP => 298.IN0
DNUP => 300.IN0
GN => 301.DATAIN
A => 255.IN0
A => 164.IN1
A => 195.IN0
SETN => 255.IN1
SETN => 253.IN1
SETN => 259.IN1
SETN => 257.IN1
SETN => 263.IN1
SETN => 261.IN1
SETN => 267.IN1
SETN => 265.IN1
SETN => 271.IN1
SETN => 269.IN1
SETN => 275.IN1
SETN => 273.IN1
SETN => 279.IN1
SETN => 277.IN1
SETN => 283.IN1
SETN => 281.IN1
CLRN => 165.IN1
CLRN => 169.IN1
CLRN => 173.IN1
CLRN => 177.IN1
CLRN => 181.IN1
CLRN => 185.IN1
CLRN => 189.IN1
CLRN => 193.IN1
CLK => 8.CLK
CLK => 7.CLK
CLK => 6.CLK
CLK => 5.CLK
CLK => 4.CLK
CLK => 3.CLK
CLK => 2.CLK
CLK => 1.CLK
LDN => 197.IN0
LDN => 205.IN0
LDN => 211.IN0
LDN => 217.IN0
LDN => 223.IN0
LDN => 228.IN0
LDN => 234.IN0
LDN => 241.IN0
B => 259.IN0
B => 168.IN1
B => 202.IN0
C => 263.IN0
C => 172.IN1
C => 208.IN0
D => 267.IN0
D => 176.IN1
D => 214.IN0
E => 271.IN0
E => 180.IN1
E => 220.IN0
F => 275.IN0
F => 184.IN1
F => 226.IN0
G => 279.IN0
G => 188.IN1
G => 232.IN0
H => 283.IN0
H => 192.IN1
H => 238.IN0
QH <= 1.DB_MAX_OUTPUT_PORT_TYPE
QG <= 2.DB_MAX_OUTPUT_PORT_TYPE
QF <= 3.DB_MAX_OUTPUT_PORT_TYPE
QE <= 4.DB_MAX_OUTPUT_PORT_TYPE
QD <= 5.DB_MAX_OUTPUT_PORT_TYPE
QC <= 6.DB_MAX_OUTPUT_PORT_TYPE
QB <= 7.DB_MAX_OUTPUT_PORT_TYPE
QA <= 8.DB_MAX_OUTPUT_PORT_TYPE
|CHRONO|DiviseurDeFrequence:inst1|7456:inst7
QA <= 5.DB_MAX_OUTPUT_PORT_TYPE
CLR => 10.IN0
CLKA => 23.IN0
QC <= 16.DB_MAX_OUTPUT_PORT_TYPE
CLKB => 24.IN0
QB <= 15.DB_MAX_OUTPUT_PORT_TYPE
|CHRONO|sequenceur2:inst17
COUNT <= inst4.DB_MAX_OUTPUT_PORT_TYPE
H => inst3.CLK
sbp1 => inst.IN0
sbp2 => inst1.IN1
RESET <= inst.DB_MAX_OUTPUT_PORT_TYPE
|CHRONO|BoutonPoussoir2:inst15
S <= inst3.DB_MAX_OUTPUT_PORT_TYPE
BPs <= inst.DB_MAX_OUTPUT_PORT_TYPE
H => inst.CLK
H => inst5.CLK
BP => inst1.IN0
|CHRONO|BoutonPoussoir2:inst16
S <= inst3.DB_MAX_OUTPUT_PORT_TYPE
BPs <= inst.DB_MAX_OUTPUT_PORT_TYPE
H => inst.CLK
H => inst5.CLK
BP => inst1.IN0

729
SLEA/db/Chronometre.hif Normal file
View file

@ -0,0 +1,729 @@
Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
18
1161
OFF
OFF
OFF
ON
ON
OFF
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Library Paths --
-- End Library Paths --
-- Start VHDL Libraries --
-- End VHDL Libraries --
# entity
7446
# storage
db|Chronometre.(1).cnf
db|Chronometre.(1).cnf
# case_insensitive
# source_file
c:|altera|90sp2|quartus|libraries|others|maxplus2|7446.bdf
e82f7e1987a7ce721115e22db681be2
26
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# hierarchies {
CheminDeDonnees:inst|7446:inst7
CheminDeDonnees:inst|7446:inst4
}
# macro_sequence
# end
# entity
8count
# storage
db|Chronometre.(3).cnf
db|Chronometre.(3).cnf
# case_insensitive
# source_file
c:|altera|90sp2|quartus|libraries|others|maxplus2|8count.tdf
2a6a409f4755d532381d1c9793829131
7
# user_parameter {
DEVICE_FAMILY
FLEX10K
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
LDN
-1
3
GN
-1
3
COUT
-1
3
CLK
-1
3
G
-1
1
F
-1
1
D
-1
1
B
-1
1
SETN
-1
2
H
-1
2
E
-1
2
DNUP
-1
2
CLRN
-1
2
C
-1
2
A
-1
2
}
# include_file {
c:|altera|90sp2|quartus|libraries|megafunctions|aglobal.inc
99832fdf63412df51d7531202d74e75
}
# macro_sequence
# end
# entity
f8count
# storage
db|Chronometre.(4).cnf
db|Chronometre.(4).cnf
# case_insensitive
# source_file
c:|altera|90sp2|quartus|libraries|others|maxplus2|f8count.bdf
cda638cfe238a883162438ebfb199e21
26
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# hierarchies {
DiviseurDeFrequence:inst1|8count:inst4|f8count:sub
DiviseurDeFrequence:inst1|8count:inst|f8count:sub
}
# macro_sequence
# end
# entity
8count
# storage
db|Chronometre.(5).cnf
db|Chronometre.(5).cnf
# case_insensitive
# source_file
c:|altera|90sp2|quartus|libraries|others|maxplus2|8count.tdf
2a6a409f4755d532381d1c9793829131
7
# user_parameter {
DEVICE_FAMILY
FLEX10K
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
LDN
-1
3
COUT
-1
3
CLK
-1
3
GN
-1
1
G
-1
1
C
-1
1
B
-1
1
SETN
-1
2
H
-1
2
F
-1
2
E
-1
2
DNUP
-1
2
D
-1
2
CLRN
-1
2
A
-1
2
}
# include_file {
c:|altera|90sp2|quartus|libraries|megafunctions|aglobal.inc
99832fdf63412df51d7531202d74e75
}
# macro_sequence
# end
# entity
7456
# storage
db|Chronometre.(6).cnf
db|Chronometre.(6).cnf
# case_insensitive
# source_file
c:|altera|90sp2|quartus|libraries|others|maxplus2|7456.bdf
c5ca1d38ffa447e5671fca116dcc73
26
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# hierarchies {
DiviseurDeFrequence:inst1|7456:inst7
}
# macro_sequence
# end
# entity
8count
# storage
db|Chronometre.(7).cnf
db|Chronometre.(7).cnf
# case_insensitive
# source_file
c:|altera|90sp2|quartus|libraries|others|maxplus2|8count.tdf
2a6a409f4755d532381d1c9793829131
7
# user_parameter {
DEVICE_FAMILY
FLEX10K
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
LDN
-1
3
GN
-1
3
COUT
-1
3
CLK
-1
3
G
-1
1
F
-1
1
B
-1
1
SETN
-1
2
H
-1
2
E
-1
2
DNUP
-1
2
D
-1
2
CLRN
-1
2
C
-1
2
A
-1
2
}
# include_file {
c:|altera|90sp2|quartus|libraries|megafunctions|aglobal.inc
99832fdf63412df51d7531202d74e75
}
# macro_sequence
# end
# entity
8count
# storage
db|Chronometre.(8).cnf
db|Chronometre.(8).cnf
# case_insensitive
# source_file
c:|altera|90sp2|quartus|libraries|others|maxplus2|8count.tdf
2a6a409f4755d532381d1c9793829131
7
# user_parameter {
DEVICE_FAMILY
FLEX10K
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
LDN
-1
3
COUT
-1
3
CLK
-1
3
GN
-1
1
G
-1
1
E
-1
1
C
-1
1
B
-1
1
SETN
-1
2
H
-1
2
F
-1
2
DNUP
-1
2
D
-1
2
CLRN
-1
2
A
-1
2
}
# include_file {
c:|altera|90sp2|quartus|libraries|megafunctions|aglobal.inc
99832fdf63412df51d7531202d74e75
}
# macro_sequence
# end
# entity
8count
# storage
db|Chronometre.(9).cnf
db|Chronometre.(9).cnf
# case_insensitive
# source_file
c:|altera|90sp2|quartus|libraries|others|maxplus2|8count.tdf
2a6a409f4755d532381d1c9793829131
7
# user_parameter {
DEVICE_FAMILY
FLEX10K
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
LDN
-1
3
GN
-1
3
COUT
-1
3
CLK
-1
3
G
-1
1
F
-1
1
DNUP
-1
1
B
-1
1
SETN
-1
2
H
-1
2
E
-1
2
D
-1
2
CLRN
-1
2
C
-1
2
A
-1
2
}
# include_file {
c:|altera|90sp2|quartus|libraries|megafunctions|aglobal.inc
99832fdf63412df51d7531202d74e75
}
# hierarchies {
DiviseurDeFrequence:inst1|8count:inst4
}
# macro_sequence
# end
# entity
8count
# storage
db|Chronometre.(10).cnf
db|Chronometre.(10).cnf
# case_insensitive
# source_file
c:|altera|90sp2|quartus|libraries|others|maxplus2|8count.tdf
2a6a409f4755d532381d1c9793829131
7
# user_parameter {
DEVICE_FAMILY
FLEX10K
PARAMETER_UNKNOWN
USR
AUTO_CARRY_CHAINS
ON
AUTO_CARRY
USR
IGNORE_CARRY_BUFFERS
OFF
IGNORE_CARRY
USR
AUTO_CASCADE_CHAINS
ON
AUTO_CASCADE
USR
IGNORE_CASCADE_BUFFERS
OFF
IGNORE_CASCADE
USR
}
# used_port {
LDN
-1
3
COUT
-1
3
CLK
-1
3
GN
-1
1
G
-1
1
E
-1
1
DNUP
-1
1
C
-1
1
B
-1
1
SETN
-1
2
H
-1
2
F
-1
2
D
-1
2
CLRN
-1
2
A
-1
2
}
# include_file {
c:|altera|90sp2|quartus|libraries|megafunctions|aglobal.inc
99832fdf63412df51d7531202d74e75
}
# hierarchies {
DiviseurDeFrequence:inst1|8count:inst
}
# macro_sequence
# end
# entity
DiviseurDeFrequence
# storage
db|Chronometre.(2).cnf
db|Chronometre.(2).cnf
# case_insensitive
# source_file
DiviseurDeFrequence.bdf
de488e6d92e1758fc3d58888ba4142
26
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# hierarchies {
DiviseurDeFrequence:inst1
}
# macro_sequence
# end
# entity
74168
# storage
db|Chronometre.(11).cnf
db|Chronometre.(11).cnf
# case_insensitive
# source_file
c:|altera|90sp2|quartus|libraries|others|maxplus2|74168.bdf
65cbff18452b4bd24481c19efe8c3d
26
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# hierarchies {
CheminDeDonnees:inst|74168:inst2
CheminDeDonnees:inst|74168:inst1
CheminDeDonnees:inst|74168:inst8
}
# macro_sequence
# end
# entity
CheminDeDonnees
# storage
db|Chronometre.(12).cnf
db|Chronometre.(12).cnf
# case_insensitive
# source_file
CheminDeDonnees.bdf
a17e92775a837fe5bb01cd4d51bb055
26
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# hierarchies {
CheminDeDonnees:inst
}
# macro_sequence
# end
# entity
BoutonPoussoir2
# storage
db|Chronometre.(0).cnf
db|Chronometre.(0).cnf
# case_insensitive
# source_file
BoutonPoussoir2.bdf
a4626d4be2214372dcddd7767b61319f
26
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# hierarchies {
BoutonPoussoir2:inst15
BoutonPoussoir2:inst16
}
# macro_sequence
# end
# entity
sequenceur2
# storage
db|Chronometre.(14).cnf
db|Chronometre.(14).cnf
# case_insensitive
# source_file
sequenceur2.bdf
5936b65ce6461430c2d5e45dfda4343
26
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# hierarchies {
sequenceur2:inst17
}
# macro_sequence
# end
# entity
CHRONO
# storage
db|Chronometre.(13).cnf
db|Chronometre.(13).cnf
# case_insensitive
# source_file
CHRONO.bdf
ac82dceeb2d51fe9037f6875b72dbff
26
# internal_option {
BLOCK_DESIGN_NAMING
AUTO
}
# hierarchies {
|
}
# macro_sequence
# end
# complete

98
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<TABLE BORDER="1" cellspacing="1" cellpadding="2">
<TR valign="middle" bgcolor="#C0C0C0">
<TH>Hierarchy</TH>
<TH>Input</TH>
<TH>Constant Input</TH>
<TH>Unused Input</TH>
<TH>Floating Input</TH>
<TH>Output</TH>
<TH>Constant Output</TH>
<TH>Unused Output</TH>
<TH>Floating Output</TH>
<TH>Bidir</TH>
<TH>Constant Bidir</TH>
<TH>Unused Bidir</TH>
<TH>Input only Bidir</TH>
<TH>Output only Bidir</TH>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">inst16</TD>
<TD ALIGN="LEFT">2</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">2</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">inst15</TD>
<TD ALIGN="LEFT">2</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">2</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">inst17</TD>
<TD ALIGN="LEFT">3</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">2</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">inst1</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">1</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
<TR valign="middle">
<TD ALIGN="LEFT">inst</TD>
<TD ALIGN="LEFT">3</TD>
<TD ALIGN="LEFT">2</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">2</TD>
<TD ALIGN="LEFT">16</TD>
<TD ALIGN="LEFT">2</TD>
<TD ALIGN="LEFT">2</TD>
<TD ALIGN="LEFT">2</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
<TD ALIGN="LEFT">0</TD>
</TR>
</TABLE>

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+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Legal Partition Candidates ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; Hierarchy ; Input ; Constant Input ; Unused Input ; Floating Input ; Output ; Constant Output ; Unused Output ; Floating Output ; Bidir ; Constant Bidir ; Unused Bidir ; Input only Bidir ; Output only Bidir ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+
; inst16 ; 2 ; 1 ; 0 ; 1 ; 2 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst15 ; 2 ; 1 ; 0 ; 1 ; 2 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst17 ; 3 ; 0 ; 0 ; 0 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst1 ; 1 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ;
; inst ; 3 ; 2 ; 0 ; 2 ; 16 ; 2 ; 2 ; 2 ; 0 ; 0 ; 0 ; 0 ; 0 ;
+-----------+-------+----------------+--------------+----------------+--------+-----------------+---------------+-----------------+-------+----------------+--------------+------------------+-------------------+

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1
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v1

32
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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jan 24 17:21:56 2018 " "Info: Processing started: Wed Jan 24 17:21:56 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off Chronometre -c Chronometre " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Chronometre -c Chronometre" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "Decodeur.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file Decodeur.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 Decodeur " "Info: Found entity 1: Decodeur" { } { { "Decodeur.bdf" "" { Schematic "E:/SLEA/Decodeur.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "BoutonPoussoir.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file BoutonPoussoir.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 BoutonPoussoir " "Info: Found entity 1: BoutonPoussoir" { } { { "BoutonPoussoir.bdf" "" { Schematic "E:/SLEA/BoutonPoussoir.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "BoutonPoussoir2.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file BoutonPoussoir2.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 BoutonPoussoir2 " "Info: Found entity 1: BoutonPoussoir2" { } { { "BoutonPoussoir2.bdf" "" { Schematic "E:/SLEA/BoutonPoussoir2.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "DiviseurDeFrequence.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file DiviseurDeFrequence.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 DiviseurDeFrequence " "Info: Found entity 1: DiviseurDeFrequence" { } { { "DiviseurDeFrequence.bdf" "" { Schematic "E:/SLEA/DiviseurDeFrequence.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CheminDeDonnees.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file CheminDeDonnees.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 CheminDeDonnees " "Info: Found entity 1: CheminDeDonnees" { } { { "CheminDeDonnees.bdf" "" { Schematic "E:/SLEA/CheminDeDonnees.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Warning" "WSGN_FILE_IS_MISSING" "E:/SLEA/Sequenceur.bdf " "Warning: Can't analyze file -- file E:/SLEA/Sequenceur.bdf is missing" { } { } 0 0 "Can't analyze file -- file %1!s! is missing" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CHRONO.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file CHRONO.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 CHRONO " "Info: Found entity 1: CHRONO" { } { { "CHRONO.bdf" "" { Schematic "E:/SLEA/CHRONO.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "sequenceur2.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file sequenceur2.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 sequenceur2 " "Info: Found entity 1: sequenceur2" { } { { "sequenceur2.bdf" "" { Schematic "E:/SLEA/sequenceur2.bdf" { } } } } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 -1} } { } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_TOP" "CHRONO " "Info: Elaborating entity \"CHRONO\" for the top level hierarchy" { } { } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "CheminDeDonnees CheminDeDonnees:inst " "Info: Elaborating entity \"CheminDeDonnees\" for hierarchy \"CheminDeDonnees:inst\"" { } { { "CHRONO.bdf" "inst" { Schematic "E:/SLEA/CHRONO.bdf" { { 104 728 904 424 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7446 CheminDeDonnees:inst\|7446:inst7 " "Info: Elaborating entity \"7446\" for hierarchy \"CheminDeDonnees:inst\|7446:inst7\"" { } { { "CheminDeDonnees.bdf" "inst7" { Schematic "E:/SLEA/CheminDeDonnees.bdf" { { 112 1024 1144 272 "inst7" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "CheminDeDonnees:inst\|7446:inst7 " "Info: Elaborated megafunction instantiation \"CheminDeDonnees:inst\|7446:inst7\"" { } { { "CheminDeDonnees.bdf" "" { Schematic "E:/SLEA/CheminDeDonnees.bdf" { { 112 1024 1144 272 "inst7" "" } } } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "74168 CheminDeDonnees:inst\|74168:inst2 " "Info: Elaborating entity \"74168\" for hierarchy \"CheminDeDonnees:inst\|74168:inst2\"" { } { { "CheminDeDonnees.bdf" "inst2" { Schematic "E:/SLEA/CheminDeDonnees.bdf" { { 352 752 856 528 "inst2" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "CheminDeDonnees:inst\|74168:inst2 " "Info: Elaborated megafunction instantiation \"CheminDeDonnees:inst\|74168:inst2\"" { } { { "CheminDeDonnees.bdf" "" { Schematic "E:/SLEA/CheminDeDonnees.bdf" { { 352 752 856 528 "inst2" "" } } } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "DiviseurDeFrequence DiviseurDeFrequence:inst1 " "Info: Elaborating entity \"DiviseurDeFrequence\" for hierarchy \"DiviseurDeFrequence:inst1\"" { } { { "CHRONO.bdf" "inst1" { Schematic "E:/SLEA/CHRONO.bdf" { { 264 360 456 360 "inst1" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "8count DiviseurDeFrequence:inst1\|8count:inst4 " "Info: Elaborating entity \"8count\" for hierarchy \"DiviseurDeFrequence:inst1\|8count:inst4\"" { } { { "DiviseurDeFrequence.bdf" "inst4" { Schematic "E:/SLEA/DiviseurDeFrequence.bdf" { { 136 728 848 392 "inst4" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "DiviseurDeFrequence:inst1\|8count:inst4 " "Info: Elaborated megafunction instantiation \"DiviseurDeFrequence:inst1\|8count:inst4\"" { } { { "DiviseurDeFrequence.bdf" "" { Schematic "E:/SLEA/DiviseurDeFrequence.bdf" { { 136 728 848 392 "inst4" "" } } } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "f8count DiviseurDeFrequence:inst1\|8count:inst4\|f8count:sub " "Info: Elaborating entity \"f8count\" for hierarchy \"DiviseurDeFrequence:inst1\|8count:inst4\|f8count:sub\"" { } { { "8count.tdf" "sub" { Text "c:/altera/90sp2/quartus/libraries/others/maxplus2/8count.tdf" 44 3 0 } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_MEGAFN_DESCENDANT" "DiviseurDeFrequence:inst1\|8count:inst4\|f8count:sub DiviseurDeFrequence:inst1\|8count:inst4 " "Info: Elaborated megafunction instantiation \"DiviseurDeFrequence:inst1\|8count:inst4\|f8count:sub\", which is child of megafunction instantiation \"DiviseurDeFrequence:inst1\|8count:inst4\"" { } { { "8count.tdf" "" { Text "c:/altera/90sp2/quartus/libraries/others/maxplus2/8count.tdf" 44 3 0 } } { "DiviseurDeFrequence.bdf" "" { Schematic "E:/SLEA/DiviseurDeFrequence.bdf" { { 136 728 848 392 "inst4" "" } } } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\", which is child of megafunction instantiation \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "8count DiviseurDeFrequence:inst1\|8count:inst " "Info: Elaborating entity \"8count\" for hierarchy \"DiviseurDeFrequence:inst1\|8count:inst\"" { } { { "DiviseurDeFrequence.bdf" "inst" { Schematic "E:/SLEA/DiviseurDeFrequence.bdf" { { 136 440 560 392 "inst" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "DiviseurDeFrequence:inst1\|8count:inst " "Info: Elaborated megafunction instantiation \"DiviseurDeFrequence:inst1\|8count:inst\"" { } { { "DiviseurDeFrequence.bdf" "" { Schematic "E:/SLEA/DiviseurDeFrequence.bdf" { { 136 440 560 392 "inst" "" } } } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "7456 DiviseurDeFrequence:inst1\|7456:inst7 " "Info: Elaborating entity \"7456\" for hierarchy \"DiviseurDeFrequence:inst1\|7456:inst7\"" { } { { "DiviseurDeFrequence.bdf" "inst7" { Schematic "E:/SLEA/DiviseurDeFrequence.bdf" { { 424 184 288 504 "inst7" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_ELABORATION_HEADER" "DiviseurDeFrequence:inst1\|7456:inst7 " "Info: Elaborated megafunction instantiation \"DiviseurDeFrequence:inst1\|7456:inst7\"" { } { { "DiviseurDeFrequence.bdf" "" { Schematic "E:/SLEA/DiviseurDeFrequence.bdf" { { 424 184 288 504 "inst7" "" } } } } } 0 0 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sequenceur2 sequenceur2:inst17 " "Info: Elaborating entity \"sequenceur2\" for hierarchy \"sequenceur2:inst17\"" { } { { "CHRONO.bdf" "inst17" { Schematic "E:/SLEA/CHRONO.bdf" { { 112 504 624 208 "inst17" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "BoutonPoussoir2 BoutonPoussoir2:inst15 " "Info: Elaborating entity \"BoutonPoussoir2\" for hierarchy \"BoutonPoussoir2:inst15\"" { } { { "CHRONO.bdf" "inst15" { Schematic "E:/SLEA/CHRONO.bdf" { { 24 360 456 120 "inst15" "" } } } } } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "" 0 -1}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "pointSeconde VCC " "Warning (13410): Pin \"pointSeconde\" is stuck at VCC" { } { { "CHRONO.bdf" "" { Schematic "E:/SLEA/CHRONO.bdf" { { 136 64 240 152 "pointSeconde" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} { "Warning" "WOPT_MLS_STUCK_PIN" "pointDixieme GND " "Warning (13410): Pin \"pointDixieme\" is stuck at GND" { } { { "CHRONO.bdf" "" { Schematic "E:/SLEA/CHRONO.bdf" { { 168 64 240 184 "pointDixieme" "" } } } } } 0 13410 "Pin \"%1!s!\" is stuck at %2!s!" 0 0 "" 0 -1} } { } 0 0 "Output pins are stuck at VCC or GND" 0 0 "" 0 -1}
{ "Info" "IFTM_CARRY_SINGLE_TO_DOUBLE" "2 " "Info: Converted 2 single input CARRY primitives to CARRY_SUM primitives" { } { } 0 0 "Converted %1!d! single input CARRY primitives to CARRY_SUM primitives" 0 0 "" 0 -1}
{ "Info" "ICUT_CUT_TM_SUMMARY" "91 " "Info: Implemented 91 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Info: Implemented 3 input pins" { } { } 0 0 "Implemented %1!d! input pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_OPINS" "19 " "Info: Implemented 19 output pins" { } { } 0 0 "Implemented %1!d! output pins" 0 0 "" 0 -1} { "Info" "ICUT_CUT_TM_LCELLS" "69 " "Info: Implemented 69 logic cells" { } { } 0 0 "Implemented %1!d! logic cells" 0 0 "" 0 -1} } { } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 4 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "199 " "Info: Peak virtual memory: 199 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jan 24 17:21:59 2018 " "Info: Processing ended: Wed Jan 24 17:21:59 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:02 " "Info: Total CPU time (on all processors): 00:00:02" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}

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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Simulator Quartus II " "Info: Running Quartus II Simulator" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jan 24 16:29:11 2018 " "Info: Processing started: Wed Jan 24 16:29:11 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sim --read_settings_files=on --write_settings_files=off Chronometre -c Chronometre " "Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off Chronometre -c Chronometre" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "ISDB_SOURCE_VECTOR_FILE_USED" "U:/SLEA/sequenceur2.vwf " "Info: Using vector source file \"U:/SLEA/sequenceur2.vwf\"" { } { } 0 0 "Using vector source file \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "ISDB_OVERWRITE_WAVEFORM_INPUTS_WITH_SIMULATION_OUTPUTS" "" "Info: Overwriting simulation input file with simulation results" { { "Info" "ISDB_SOURCE_VECTOR_FILE_BACKUP" "sequenceur2.vwf Chronometre.sim_ori.vwf " "Info: A backup of sequenceur2.vwf called Chronometre.sim_ori.vwf has been created in the db folder" { } { } 0 0 "A backup of %1!s! called %2!s! has been created in the db folder" 0 0 "" 0 -1} } { } 0 0 "Overwriting simulation input file with simulation results" 0 0 "" 0 -1}
{ "Info" "IEDS_MAX_TRANSITION_COUNT" "" "Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled" { { "Info" "IEDS_MAX_TRANSITION_COUNT_EXP" "" "Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." { } { } 0 0 "Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements." 0 0 "" 0 -1} } { } 0 0 "Option to preserve fewer signal transitions to reduce memory requirements is enabled" 0 0 "" 0 -1}
{ "Warning" "WSDB_CLOCK_SENSITIVE_CHANGE" "\|sequenceur2\|inst3 10.0 ms " "Warning: Found clock-sensitive change during active clock edge at time 10.0 ms on register \"\|sequenceur2\|inst3\"" { } { } 0 0 "Found clock-sensitive change during active clock edge at time %2!s! on register \"%1!s!\"" 0 0 "" 0 -1}
{ "Info" "IEDS_SUB_SIMULATION_COUNT" "1 " "Info: Simulation partitioned into 1 sub-simulations" { } { } 0 0 "Simulation partitioned into %1!d! sub-simulations" 0 0 "" 0 -1}
{ "Info" "ISIM_SIM_SIMULATION_COVERAGE" " 100.00 % " "Info: Simulation coverage is 100.00 %" { } { } 0 0 "Simulation coverage is %1!s!" 0 0 "" 0 -1}
{ "Info" "ISIM_SIM_NUMBER_OF_TRANSITION" "57 " "Info: Number of transitions in simulation is 57" { } { } 0 0 "Number of transitions in simulation is %1!s!" 0 0 "" 0 -1}
{ "Info" "ISDB_SDB_PROMOTE_WRITE_BINARY_VECTOR" "sequenceur2.vwf " "Info: Vector file sequenceur2.vwf is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help." { } { } 0 0 "Vector file %1!s! is saved in VWF text format. You can compress it into CVWF format in order to reduce file size. For more details please refer to the Quartus II Help." 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Simulator 0 s 1 Quartus II " "Info: Quartus II Simulator was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "134 " "Info: Peak virtual memory: 134 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jan 24 16:29:12 2018 " "Info: Processing ended: Wed Jan 24 16:29:12 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}

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/*
WARNING: Do NOT edit the input and output ports in this file in a text
editor if you plan to continue editing the block that represents it in
the Block Editor! File corruption is VERY likely to occur.
*/
/*
Copyright (C) 1991-2009 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files from any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
*/
HEADER
{
VERSION = 1;
TIME_UNIT = ns;
DATA_OFFSET = 0.0;
DATA_DURATION = 100000000.0;
SIMULATION_TIME = 100000000.0;
GRID_PHASE = 0.0;
GRID_PERIOD = 5000000.0;
GRID_DUTY_CYCLE = 50;
}
SIGNAL("COUNT")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("H")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("RESET")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = OUTPUT;
PARENT = "";
}
SIGNAL("sbp1")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
SIGNAL("sbp2")
{
VALUE_TYPE = NINE_LEVEL_BIT;
SIGNAL_TYPE = SINGLE_BIT;
WIDTH = 1;
LSB_INDEX = -1;
DIRECTION = INPUT;
PARENT = "";
}
TRANSITION_LIST("COUNT")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 10000000.0;
LEVEL 0 FOR 40000000.0;
LEVEL 1 FOR 50000000.0;
}
}
TRANSITION_LIST("H")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 5000000.0;
LEVEL 0 FOR 5000000.0;
LEVEL 1 FOR 5000000.0;
LEVEL 0 FOR 5000000.0;
LEVEL 1 FOR 5000000.0;
LEVEL 0 FOR 5000000.0;
LEVEL 1 FOR 5000000.0;
LEVEL 0 FOR 5000000.0;
LEVEL 1 FOR 5000000.0;
LEVEL 0 FOR 5000000.0;
LEVEL 1 FOR 5000000.0;
LEVEL 0 FOR 5000000.0;
LEVEL 1 FOR 5000000.0;
LEVEL 0 FOR 5000000.0;
LEVEL 1 FOR 5000000.0;
LEVEL 0 FOR 5000000.0;
LEVEL 1 FOR 5000000.0;
LEVEL 0 FOR 5000000.0;
LEVEL 1 FOR 5000000.0;
LEVEL 0 FOR 5000000.0;
}
}
TRANSITION_LIST("RESET")
{
NODE
{
REPEAT = 1;
LEVEL 1 FOR 50000000.0;
LEVEL 0 FOR 10000000.0;
LEVEL 1 FOR 40000000.0;
}
}
TRANSITION_LIST("sbp1")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 70000000.0;
LEVEL 1 FOR 10000000.0;
LEVEL 0 FOR 20000000.0;
}
}
TRANSITION_LIST("sbp2")
{
NODE
{
REPEAT = 1;
LEVEL 0 FOR 10000000.0;
LEVEL 1 FOR 10000000.0;
LEVEL 0 FOR 10000000.0;
LEVEL 1 FOR 10000000.0;
LEVEL 0 FOR 10000000.0;
LEVEL 1 FOR 10000000.0;
LEVEL 0 FOR 40000000.0;
}
}
DISPLAY_LINE
{
CHANNEL = "COUNT";
EXPAND_STATUS = COLLAPSED;
RADIX = ASCII;
TREE_INDEX = 0;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "H";
EXPAND_STATUS = COLLAPSED;
RADIX = ASCII;
TREE_INDEX = 1;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "RESET";
EXPAND_STATUS = COLLAPSED;
RADIX = ASCII;
TREE_INDEX = 2;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "sbp1";
EXPAND_STATUS = COLLAPSED;
RADIX = ASCII;
TREE_INDEX = 3;
TREE_LEVEL = 0;
}
DISPLAY_LINE
{
CHANNEL = "sbp2";
EXPAND_STATUS = COLLAPSED;
RADIX = ASCII;
TREE_INDEX = 4;
TREE_LEVEL = 0;
}
TIME_BAR
{
TIME = 27800;
MASTER = TRUE;
}
;

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BOF
EOF

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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "TimeQuest Timing Analyzer Quartus II " "Info: Running Quartus II TimeQuest Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Fri Dec 08 14:50:29 2017 " "Info: Processing started: Fri Dec 08 14:50:29 2017" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_sta Chronometre -c Chronometre " "Info: Command: quartus_sta Chronometre -c Chronometre" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "0" "" "Info: qsta_default_script.tcl version: #1" { } { } 0 0 "qsta_default_script.tcl version: #1" 0 0 "" 0 -1}
{ "Error" "0" "" "Error: FLEX10K Device family is not supported by the TimeQuest Timing Analyzer." { } { } 0 0 "FLEX10K Device family is not supported by the TimeQuest Timing Analyzer." 0 0 "" 0 -1}

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