klafyvel/SLEA-chrono
1
0
Fork 0
Code Issues Pull requests Releases Wiki Activity
SLEA-chrono/SLEA/db/prev_cmp_Chronometre.tan.qmsg
Klafyvel 4cd8f015ee Séance du 24/01
2018-01-24 17:28:00 +01:00

12 lines
60 KiB
Text
Raw Blame History

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition " "Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Jan 24 17:20:53 2018 " "Info: Processing started: Wed Jan 24 17:20:53 2018" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off Chronometre -c Chronometre " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Chronometre -c Chronometre" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "H " "Info: Assuming node \"H\" is an undefined clock" { } { { "CHRONO.bdf" "" { Schematic "E:/SLEA/CHRONO.bdf" { { 24 64 232 40 "H" "" } { 280 320 360 296 "H" "" } } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "H" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "DiviseurDeFrequence:inst1\|7456:inst7\|5 " "Info: Detected ripple clock \"DiviseurDeFrequence:inst1\|7456:inst7\|5\" as buffer" { } { { "7456.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/7456.bdf" { { 328 344 408 408 "5" "" } } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DiviseurDeFrequence:inst1\|7456:inst7\|5" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} { "Info" "ITAN_RIPPLE_CLK" "DiviseurDeFrequence:inst1\|inst10 " "Info: Detected ripple clock \"DiviseurDeFrequence:inst1\|inst10\" as buffer" { } { { "DiviseurDeFrequence.bdf" "" { Schematic "E:/SLEA/DiviseurDeFrequence.bdf" { { 312 1216 1280 392 "inst10" "" } } } } { "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" "" { Assignment "c:/altera/90sp2/quartus/bin/Assignment Editor.qase" 1 { { 0 "DiviseurDeFrequence:inst1\|inst10" } } } } } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0 -1} } { } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "H register DiviseurDeFrequence:inst1\|8count:inst\|f8count:sub\|8 register DiviseurDeFrequence:inst1\|8count:inst4\|f8count:sub\|2 42.02 MHz 23.8 ns Internal " "Info: Clock \"H\" has Internal fmax of 42.02 MHz between source register \"DiviseurDeFrequence:inst1\|8count:inst\|f8count:sub\|8\" and destination register \"DiviseurDeFrequence:inst1\|8count:inst4\|f8count:sub\|2\" (period= 23.8 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "19.700 ns + Longest register register " "Info: + Longest register to register delay is 19.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DiviseurDeFrequence:inst1\|8count:inst\|f8count:sub\|8 1 REG LC5_H27 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_H27; Fanout = 2; REG Node = 'DiviseurDeFrequence:inst1\|8count:inst\|f8count:sub\|8'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 } "NODE_NAME" } } { "f8count.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/f8count.bdf" { { 448 1728 1792 528 "8" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.500 ns) 1.500 ns DiviseurDeFrequence:inst1\|8count:inst\|f8count:sub\|245 2 COMB LC5_H27 2 " "Info: 2: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = LC5_H27; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1\|8count:inst\|f8count:sub\|245'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.500 ns" { DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 DiviseurDeFrequence:inst1|8count:inst|f8count:sub|245 } "NODE_NAME" } } { "f8count.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/f8count.bdf" { { 608 1128 1176 640 "245" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 1.800 ns DiviseurDeFrequence:inst1\|8count:inst\|f8count:sub\|246 3 COMB LC6_H27 2 " "Info: 3: + IC(0.000 ns) + CELL(0.300 ns) = 1.800 ns; Loc. = LC6_H27; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1\|8count:inst\|f8count:sub\|246'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.300 ns" { DiviseurDeFrequence:inst1|8count:inst|f8count:sub|245 DiviseurDeFrequence:inst1|8count:inst|f8count:sub|246 } "NODE_NAME" } } { "f8count.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/f8count.bdf" { { 920 1128 1176 952 "246" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 2.100 ns DiviseurDeFrequence:inst1\|8count:inst\|f8count:sub\|247 4 COMB LC7_H27 2 " "Info: 4: + IC(0.000 ns) + CELL(0.300 ns) = 2.100 ns; Loc. = LC7_H27; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1\|8count:inst\|f8count:sub\|247'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.300 ns" { DiviseurDeFrequence:inst1|8count:inst|f8count:sub|246 DiviseurDeFrequence:inst1|8count:inst|f8count:sub|247 } "NODE_NAME" } } { "f8count.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/f8count.bdf" { { 1232 1128 1176 1264 "247" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 2.400 ns DiviseurDeFrequence:inst1\|8count:inst\|f8count:sub\|248 5 COMB LC8_H27 2 " "Info: 5: + IC(0.000 ns) + CELL(0.300 ns) = 2.400 ns; Loc. = LC8_H27; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1\|8count:inst\|f8count:sub\|248'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.300 ns" { DiviseurDeFrequence:inst1|8count:inst|f8count:sub|247 DiviseurDeFrequence:inst1|8count:inst|f8count:sub|248 } "NODE_NAME" } } { "f8count.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/f8count.bdf" { { 1528 1128 1176 1560 "248" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(0.300 ns) 3.800 ns DiviseurDeFrequence:inst1\|8count:inst\|f8count:sub\|249 6 COMB LC1_H29 2 " "Info: 6: + IC(1.100 ns) + CELL(0.300 ns) = 3.800 ns; Loc. = LC1_H29; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1\|8count:inst\|f8count:sub\|249'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { DiviseurDeFrequence:inst1|8count:inst|f8count:sub|248 DiviseurDeFrequence:inst1|8count:inst|f8count:sub|249 } "NODE_NAME" } } { "f8count.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/f8count.bdf" { { 1840 1128 1176 1872 "249" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 4.100 ns DiviseurDeFrequence:inst1\|8count:inst\|f8count:sub\|250 7 COMB LC2_H29 2 " "Info: 7: + IC(0.000 ns) + CELL(0.300 ns) = 4.100 ns; Loc. = LC2_H29; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1\|8count:inst\|f8count:sub\|250'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.300 ns" { DiviseurDeFrequence:inst1|8count:inst|f8count:sub|249 DiviseurDeFrequence:inst1|8count:inst|f8count:sub|250 } "NODE_NAME" } } { "f8count.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/f8count.bdf" { { 2152 1128 1176 2184 "250" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 4.400 ns DiviseurDeFrequence:inst1\|8count:inst\|f8count:sub\|251 8 COMB LC3_H29 2 " "Info: 8: + IC(0.000 ns) + CELL(0.300 ns) = 4.400 ns; Loc. = LC3_H29; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1\|8count:inst\|f8count:sub\|251'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.300 ns" { DiviseurDeFrequence:inst1|8count:inst|f8count:sub|250 DiviseurDeFrequence:inst1|8count:inst|f8count:sub|251 } "NODE_NAME" } } { "f8count.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/f8count.bdf" { { 2464 1128 1176 2496 "251" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 4.700 ns DiviseurDeFrequence:inst1\|8count:inst\|f8count:sub\|302 9 COMB LC4_H29 2 " "Info: 9: + IC(0.000 ns) + CELL(0.300 ns) = 4.700 ns; Loc. = LC4_H29; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1\|8count:inst\|f8count:sub\|302'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.300 ns" { DiviseurDeFrequence:inst1|8count:inst|f8count:sub|251 DiviseurDeFrequence:inst1|8count:inst|f8count:sub|302 } "NODE_NAME" } } { "f8count.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/f8count.bdf" { { 2768 1176 1224 2800 "302" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 5.000 ns DiviseurDeFrequence:inst1\|8count:inst4\|f8count:sub\|245 10 COMB LC5_H29 2 " "Info: 10: + IC(0.000 ns) + CELL(0.300 ns) = 5.000 ns; Loc. = LC5_H29; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1\|8count:inst4\|f8count:sub\|245'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.300 ns" { DiviseurDeFrequence:inst1|8count:inst|f8count:sub|302 DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|245 } "NODE_NAME" } } { "f8count.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/f8count.bdf" { { 608 1128 1176 640 "245" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 5.300 ns DiviseurDeFrequence:inst1\|8count:inst4\|f8count:sub\|246 11 COMB LC6_H29 2 " "Info: 11: + IC(0.000 ns) + CELL(0.300 ns) = 5.300 ns; Loc. = LC6_H29; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1\|8count:inst4\|f8count:sub\|246'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.300 ns" { DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|245 DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|246 } "NODE_NAME" } } { "f8count.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/f8count.bdf" { { 920 1128 1176 952 "246" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 5.600 ns DiviseurDeFrequence:inst1\|8count:inst4\|f8count:sub\|247 12 COMB LC7_H29 2 " "Info: 12: + IC(0.000 ns) + CELL(0.300 ns) = 5.600 ns; Loc. = LC7_H29; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1\|8count:inst4\|f8count:sub\|247'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.300 ns" { DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|246 DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|247 } "NODE_NAME" } } { "f8count.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/f8count.bdf" { { 1232 1128 1176 1264 "247" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 5.900 ns DiviseurDeFrequence:inst1\|8count:inst4\|f8count:sub\|248 13 COMB LC8_H29 2 " "Info: 13: + IC(0.000 ns) + CELL(0.300 ns) = 5.900 ns; Loc. = LC8_H29; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1\|8count:inst4\|f8count:sub\|248'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.300 ns" { DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|247 DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|248 } "NODE_NAME" } } { "f8count.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/f8count.bdf" { { 1528 1128 1176 1560 "248" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(0.300 ns) 7.300 ns DiviseurDeFrequence:inst1\|8count:inst4\|f8count:sub\|249 14 COMB LC1_H31 2 " "Info: 14: + IC(1.100 ns) + CELL(0.300 ns) = 7.300 ns; Loc. = LC1_H31; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1\|8count:inst4\|f8count:sub\|249'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.400 ns" { DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|248 DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|249 } "NODE_NAME" } } { "f8count.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/f8count.bdf" { { 1840 1128 1176 1872 "249" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 7.600 ns DiviseurDeFrequence:inst1\|8count:inst4\|f8count:sub\|250 15 COMB LC2_H31 2 " "Info: 15: + IC(0.000 ns) + CELL(0.300 ns) = 7.600 ns; Loc. = LC2_H31; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1\|8count:inst4\|f8count:sub\|250'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.300 ns" { DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|249 DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|250 } "NODE_NAME" } } { "f8count.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/f8count.bdf" { { 2152 1128 1176 2184 "250" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 7.900 ns DiviseurDeFrequence:inst1\|8count:inst4\|f8count:sub\|251 16 COMB LC3_H31 2 " "Info: 16: + IC(0.000 ns) + CELL(0.300 ns) = 7.900 ns; Loc. = LC3_H31; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1\|8count:inst4\|f8count:sub\|251'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.300 ns" { DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|250 DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|251 } "NODE_NAME" } } { "f8count.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/f8count.bdf" { { 2464 1128 1176 2496 "251" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.300 ns) 8.200 ns DiviseurDeFrequence:inst1\|8count:inst4\|f8count:sub\|302 17 COMB LC4_H31 1 " "Info: 17: + IC(0.000 ns) + CELL(0.300 ns) = 8.200 ns; Loc. = LC4_H31; Fanout = 1; COMB Node = 'DiviseurDeFrequence:inst1\|8count:inst4\|f8count:sub\|302'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "0.300 ns" { DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|251 DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|302 } "NODE_NAME" } } { "f8count.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/f8count.bdf" { { 2768 1176 1224 2800 "302" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 9.400 ns DiviseurDeFrequence:inst1\|8count:inst4\|f8count:sub\|302~5 18 COMB LC5_H31 11 " "Info: 18: + IC(0.000 ns) + CELL(1.200 ns) = 9.400 ns; Loc. = LC5_H31; Fanout = 11; COMB Node = 'DiviseurDeFrequence:inst1\|8count:inst4\|f8count:sub\|302~5'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "1.200 ns" { DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|302 DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|302~5 } "NODE_NAME" } } { "f8count.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/f8count.bdf" { { 2768 1176 1224 2800 "302" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.900 ns) + CELL(2.400 ns) 14.700 ns DiviseurDeFrequence:inst1\|8count:inst4\|f8count:sub\|302~5_wirecell 19 COMB LC3_H27 7 " "Info: 19: + IC(2.900 ns) + CELL(2.400 ns) = 14.700 ns; Loc. = LC3_H27; Fanout = 7; COMB Node = 'DiviseurDeFrequence:inst1\|8count:inst4\|f8count:sub\|302~5_wirecell'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.300 ns" { DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|302~5 DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|302~5_wirecell } "NODE_NAME" } } { "f8count.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/f8count.bdf" { { 2768 1176 1224 2800 "302" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.000 ns) + CELL(2.000 ns) 19.700 ns DiviseurDeFrequence:inst1\|8count:inst4\|f8count:sub\|2 20 REG LC3_H31 2 " "Info: 20: + IC(3.000 ns) + CELL(2.000 ns) = 19.700 ns; Loc. = LC3_H31; Fanout = 2; REG Node = 'DiviseurDeFrequence:inst1\|8count:inst4\|f8count:sub\|2'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.000 ns" { DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|302~5_wirecell DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 } "NODE_NAME" } } { "f8count.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/f8count.bdf" { { 2304 1728 1792 2384 "2" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "11.600 ns ( 58.88 % ) " "Info: Total cell delay = 11.600 ns ( 58.88 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "8.100 ns ( 41.12 % ) " "Info: Total interconnect delay = 8.100 ns ( 41.12 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "19.700 ns" { DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 DiviseurDeFrequence:inst1|8count:inst|f8count:sub|245 DiviseurDeFrequence:inst1|8count:inst|f8count:sub|246 DiviseurDeFrequence:inst1|8count:inst|f8count:sub|247 DiviseurDeFrequence:inst1|8count:inst|f8count:sub|248 DiviseurDeFrequence:inst1|8count:inst|f8count:sub|249 DiviseurDeFrequence:inst1|8count:inst|f8count:sub|250 DiviseurDeFrequence:inst1|8count:inst|f8count:sub|251 DiviseurDeFrequence:inst1|8count:inst|f8count:sub|302 DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|245 DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|246 DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|247 DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|248 DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|249 DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|250 DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|251 DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|302 DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|302~5 DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|302~5_wirecell DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "19.700 ns" { DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 {} DiviseurDeFrequence:inst1|8count:inst|f8count:sub|245 {} DiviseurDeFrequence:inst1|8count:inst|f8count:sub|246 {} DiviseurDeFrequence:inst1|8count:inst|f8count:sub|247 {} DiviseurDeFrequence:inst1|8count:inst|f8count:sub|248 {} DiviseurDeFrequence:inst1|8count:inst|f8count:sub|249 {} DiviseurDeFrequence:inst1|8count:inst|f8count:sub|250 {} DiviseurDeFrequence:inst1|8count:inst|f8count:sub|251 {} DiviseurDeFrequence:inst1|8count:inst|f8count:sub|302 {} DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|245 {} DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|246 {} DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|247 {} DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|248 {} DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|249 {} DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|250 {} DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|251 {} DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|302 {} DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|302~5 {} DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|302~5_wirecell {} DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 {} } { 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.100ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.100ns 0.000ns 0.000ns 0.000ns 0.000ns 2.900ns 3.000ns } { 0.000ns 1.500ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 1.200ns 2.400ns 2.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.100 ns - Smallest " "Info: - Smallest clock skew is -0.100 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "H destination 11.800 ns + Shortest register " "Info: + Shortest clock path from clock \"H\" to destination register is 11.800 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.900 ns) 2.900 ns H 1 CLK PIN_91 3 " "Info: 1: + IC(0.000 ns) + CELL(2.900 ns) = 2.900 ns; Loc. = PIN_91; Fanout = 3; CLK Node = 'H'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { H } "NODE_NAME" } } { "CHRONO.bdf" "" { Schematic "E:/SLEA/CHRONO.bdf" { { 24 64 232 40 "H" "" } { 280 320 360 296 "H" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.100 ns) + CELL(1.400 ns) 8.400 ns DiviseurDeFrequence:inst1\|7456:inst7\|5 2 REG LC1_H41 18 " "Info: 2: + IC(4.100 ns) + CELL(1.400 ns) = 8.400 ns; Loc. = LC1_H41; Fanout = 18; REG Node = 'DiviseurDeFrequence:inst1\|7456:inst7\|5'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.500 ns" { H DiviseurDeFrequence:inst1|7456:inst7|5 } "NODE_NAME" } } { "7456.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/7456.bdf" { { 328 344 408 408 "5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(0.000 ns) 11.800 ns DiviseurDeFrequence:inst1\|8count:inst4\|f8count:sub\|2 3 REG LC3_H31 2 " "Info: 3: + IC(3.400 ns) + CELL(0.000 ns) = 11.800 ns; Loc. = LC3_H31; Fanout = 2; REG Node = 'DiviseurDeFrequence:inst1\|8count:inst4\|f8count:sub\|2'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.400 ns" { DiviseurDeFrequence:inst1|7456:inst7|5 DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 } "NODE_NAME" } } { "f8count.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/f8count.bdf" { { 2304 1728 1792 2384 "2" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.300 ns ( 36.44 % ) " "Info: Total cell delay = 4.300 ns ( 36.44 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "7.500 ns ( 63.56 % ) " "Info: Total interconnect delay = 7.500 ns ( 63.56 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "11.800 ns" { H DiviseurDeFrequence:inst1|7456:inst7|5 DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "11.800 ns" { H {} H~out {} DiviseurDeFrequence:inst1|7456:inst7|5 {} DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 {} } { 0.000ns 0.000ns 4.100ns 3.400ns } { 0.000ns 2.900ns 1.400ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "H source 11.900 ns - Longest register " "Info: - Longest clock path from clock \"H\" to source register is 11.900 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.900 ns) 2.900 ns H 1 CLK PIN_91 3 " "Info: 1: + IC(0.000 ns) + CELL(2.900 ns) = 2.900 ns; Loc. = PIN_91; Fanout = 3; CLK Node = 'H'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { H } "NODE_NAME" } } { "CHRONO.bdf" "" { Schematic "E:/SLEA/CHRONO.bdf" { { 24 64 232 40 "H" "" } { 280 320 360 296 "H" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.100 ns) + CELL(1.400 ns) 8.400 ns DiviseurDeFrequence:inst1\|7456:inst7\|5 2 REG LC1_H41 18 " "Info: 2: + IC(4.100 ns) + CELL(1.400 ns) = 8.400 ns; Loc. = LC1_H41; Fanout = 18; REG Node = 'DiviseurDeFrequence:inst1\|7456:inst7\|5'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.500 ns" { H DiviseurDeFrequence:inst1|7456:inst7|5 } "NODE_NAME" } } { "7456.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/7456.bdf" { { 328 344 408 408 "5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(0.000 ns) 11.900 ns DiviseurDeFrequence:inst1\|8count:inst\|f8count:sub\|8 3 REG LC5_H27 2 " "Info: 3: + IC(3.500 ns) + CELL(0.000 ns) = 11.900 ns; Loc. = LC5_H27; Fanout = 2; REG Node = 'DiviseurDeFrequence:inst1\|8count:inst\|f8count:sub\|8'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "3.500 ns" { DiviseurDeFrequence:inst1|7456:inst7|5 DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 } "NODE_NAME" } } { "f8count.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/f8count.bdf" { { 448 1728 1792 528 "8" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.300 ns ( 36.13 % ) " "Info: Total cell delay = 4.300 ns ( 36.13 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "7.600 ns ( 63.87 % ) " "Info: Total interconnect delay = 7.600 ns ( 63.87 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "11.900 ns" { H DiviseurDeFrequence:inst1|7456:inst7|5 DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "11.900 ns" { H {} H~out {} DiviseurDeFrequence:inst1|7456:inst7|5 {} DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 {} } { 0.000ns 0.000ns 4.100ns 3.500ns } { 0.000ns 2.900ns 1.400ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "11.800 ns" { H DiviseurDeFrequence:inst1|7456:inst7|5 DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "11.800 ns" { H {} H~out {} DiviseurDeFrequence:inst1|7456:inst7|5 {} DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 {} } { 0.000ns 0.000ns 4.100ns 3.400ns } { 0.000ns 2.900ns 1.400ns 0.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "11.900 ns" { H DiviseurDeFrequence:inst1|7456:inst7|5 DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "11.900 ns" { H {} H~out {} DiviseurDeFrequence:inst1|7456:inst7|5 {} DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 {} } { 0.000ns 0.000ns 4.100ns 3.500ns } { 0.000ns 2.900ns 1.400ns 0.000ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "1.400 ns + " "Info: + Micro clock to output delay of source is 1.400 ns" { } { { "f8count.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/f8count.bdf" { { 448 1728 1792 528 "8" "" } } } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "2.600 ns + " "Info: + Micro setup delay of destination is 2.600 ns" { } { { "f8count.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/f8count.bdf" { { 2304 1728 1792 2384 "2" "" } } } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "19.700 ns" { DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 DiviseurDeFrequence:inst1|8count:inst|f8count:sub|245 DiviseurDeFrequence:inst1|8count:inst|f8count:sub|246 DiviseurDeFrequence:inst1|8count:inst|f8count:sub|247 DiviseurDeFrequence:inst1|8count:inst|f8count:sub|248 DiviseurDeFrequence:inst1|8count:inst|f8count:sub|249 DiviseurDeFrequence:inst1|8count:inst|f8count:sub|250 DiviseurDeFrequence:inst1|8count:inst|f8count:sub|251 DiviseurDeFrequence:inst1|8count:inst|f8count:sub|302 DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|245 DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|246 DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|247 DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|248 DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|249 DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|250 DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|251 DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|302 DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|302~5 DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|302~5_wirecell DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "19.700 ns" { DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 {} DiviseurDeFrequence:inst1|8count:inst|f8count:sub|245 {} DiviseurDeFrequence:inst1|8count:inst|f8count:sub|246 {} DiviseurDeFrequence:inst1|8count:inst|f8count:sub|247 {} DiviseurDeFrequence:inst1|8count:inst|f8count:sub|248 {} DiviseurDeFrequence:inst1|8count:inst|f8count:sub|249 {} DiviseurDeFrequence:inst1|8count:inst|f8count:sub|250 {} DiviseurDeFrequence:inst1|8count:inst|f8count:sub|251 {} DiviseurDeFrequence:inst1|8count:inst|f8count:sub|302 {} DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|245 {} DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|246 {} DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|247 {} DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|248 {} DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|249 {} DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|250 {} DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|251 {} DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|302 {} DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|302~5 {} DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|302~5_wirecell {} DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 {} } { 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.100ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 0.000ns 1.100ns 0.000ns 0.000ns 0.000ns 0.000ns 2.900ns 3.000ns } { 0.000ns 1.500ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 0.300ns 1.200ns 2.400ns 2.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "11.800 ns" { H DiviseurDeFrequence:inst1|7456:inst7|5 DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "11.800 ns" { H {} H~out {} DiviseurDeFrequence:inst1|7456:inst7|5 {} DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 {} } { 0.000ns 0.000ns 4.100ns 3.400ns } { 0.000ns 2.900ns 1.400ns 0.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "11.900 ns" { H DiviseurDeFrequence:inst1|7456:inst7|5 DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "11.900 ns" { H {} H~out {} DiviseurDeFrequence:inst1|7456:inst7|5 {} DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 {} } { 0.000ns 0.000ns 4.100ns 3.500ns } { 0.000ns 2.900ns 1.400ns 0.000ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1}
{ "Info" "ITDB_TSU_RESULT" "BoutonPoussoir2:inst16\|inst BP2 H 0.100 ns register " "Info: tsu for register \"BoutonPoussoir2:inst16\|inst\" (data pin = \"BP2\", clock pin = \"H\") is 0.100 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "20.200 ns + Longest pin register " "Info: + Longest pin to register delay is 20.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(10.300 ns) 10.300 ns BP2 1 PIN PIN_29 1 " "Info: 1: + IC(0.000 ns) + CELL(10.300 ns) = 10.300 ns; Loc. = PIN_29; Fanout = 1; PIN Node = 'BP2'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { BP2 } "NODE_NAME" } } { "CHRONO.bdf" "" { Schematic "E:/SLEA/CHRONO.bdf" { { 72 64 232 88 "BP2" "" } { 152 336 364 168 "BP2" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(8.200 ns) + CELL(1.700 ns) 20.200 ns BoutonPoussoir2:inst16\|inst 2 REG LC1_H32 2 " "Info: 2: + IC(8.200 ns) + CELL(1.700 ns) = 20.200 ns; Loc. = LC1_H32; Fanout = 2; REG Node = 'BoutonPoussoir2:inst16\|inst'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.900 ns" { BP2 BoutonPoussoir2:inst16|inst } "NODE_NAME" } } { "BoutonPoussoir2.bdf" "" { Schematic "E:/SLEA/BoutonPoussoir2.bdf" { { 344 912 976 424 "inst" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.000 ns ( 59.41 % ) " "Info: Total cell delay = 12.000 ns ( 59.41 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "8.200 ns ( 40.59 % ) " "Info: Total interconnect delay = 8.200 ns ( 40.59 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "20.200 ns" { BP2 BoutonPoussoir2:inst16|inst } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "20.200 ns" { BP2 {} BP2~out {} BoutonPoussoir2:inst16|inst {} } { 0.000ns 0.000ns 8.200ns } { 0.000ns 10.300ns 1.700ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "2.600 ns + " "Info: + Micro setup delay of destination is 2.600 ns" { } { { "BoutonPoussoir2.bdf" "" { Schematic "E:/SLEA/BoutonPoussoir2.bdf" { { 344 912 976 424 "inst" "" } } } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "H destination 22.700 ns - Shortest register " "Info: - Shortest clock path from clock \"H\" to destination register is 22.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.900 ns) 2.900 ns H 1 CLK PIN_91 3 " "Info: 1: + IC(0.000 ns) + CELL(2.900 ns) = 2.900 ns; Loc. = PIN_91; Fanout = 3; CLK Node = 'H'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { H } "NODE_NAME" } } { "CHRONO.bdf" "" { Schematic "E:/SLEA/CHRONO.bdf" { { 24 64 232 40 "H" "" } { 280 320 360 296 "H" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.100 ns) + CELL(1.400 ns) 8.400 ns DiviseurDeFrequence:inst1\|7456:inst7\|5 2 REG LC1_H41 18 " "Info: 2: + IC(4.100 ns) + CELL(1.400 ns) = 8.400 ns; Loc. = LC1_H41; Fanout = 18; REG Node = 'DiviseurDeFrequence:inst1\|7456:inst7\|5'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.500 ns" { H DiviseurDeFrequence:inst1|7456:inst7|5 } "NODE_NAME" } } { "7456.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/7456.bdf" { { 328 344 408 408 "5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(1.400 ns) 13.300 ns DiviseurDeFrequence:inst1\|inst10 3 REG LC1_H27 18 " "Info: 3: + IC(3.500 ns) + CELL(1.400 ns) = 13.300 ns; Loc. = LC1_H27; Fanout = 18; REG Node = 'DiviseurDeFrequence:inst1\|inst10'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.900 ns" { DiviseurDeFrequence:inst1|7456:inst7|5 DiviseurDeFrequence:inst1|inst10 } "NODE_NAME" } } { "DiviseurDeFrequence.bdf" "" { Schematic "E:/SLEA/DiviseurDeFrequence.bdf" { { 312 1216 1280 392 "inst10" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(9.400 ns) + CELL(0.000 ns) 22.700 ns BoutonPoussoir2:inst16\|inst 4 REG LC1_H32 2 " "Info: 4: + IC(9.400 ns) + CELL(0.000 ns) = 22.700 ns; Loc. = LC1_H32; Fanout = 2; REG Node = 'BoutonPoussoir2:inst16\|inst'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.400 ns" { DiviseurDeFrequence:inst1|inst10 BoutonPoussoir2:inst16|inst } "NODE_NAME" } } { "BoutonPoussoir2.bdf" "" { Schematic "E:/SLEA/BoutonPoussoir2.bdf" { { 344 912 976 424 "inst" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.700 ns ( 25.11 % ) " "Info: Total cell delay = 5.700 ns ( 25.11 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "17.000 ns ( 74.89 % ) " "Info: Total interconnect delay = 17.000 ns ( 74.89 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "22.700 ns" { H DiviseurDeFrequence:inst1|7456:inst7|5 DiviseurDeFrequence:inst1|inst10 BoutonPoussoir2:inst16|inst } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "22.700 ns" { H {} H~out {} DiviseurDeFrequence:inst1|7456:inst7|5 {} DiviseurDeFrequence:inst1|inst10 {} BoutonPoussoir2:inst16|inst {} } { 0.000ns 0.000ns 4.100ns 3.500ns 9.400ns } { 0.000ns 2.900ns 1.400ns 1.400ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "20.200 ns" { BP2 BoutonPoussoir2:inst16|inst } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "20.200 ns" { BP2 {} BP2~out {} BoutonPoussoir2:inst16|inst {} } { 0.000ns 0.000ns 8.200ns } { 0.000ns 10.300ns 1.700ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "22.700 ns" { H DiviseurDeFrequence:inst1|7456:inst7|5 DiviseurDeFrequence:inst1|inst10 BoutonPoussoir2:inst16|inst } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "22.700 ns" { H {} H~out {} DiviseurDeFrequence:inst1|7456:inst7|5 {} DiviseurDeFrequence:inst1|inst10 {} BoutonPoussoir2:inst16|inst {} } { 0.000ns 0.000ns 4.100ns 3.500ns 9.400ns } { 0.000ns 2.900ns 1.400ns 1.400ns 0.000ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_FULL_TCO_RESULT" "H b1 CheminDeDonnees:inst\|74168:inst1\|49 40.800 ns register " "Info: tco from clock \"H\" to destination pin \"b1\" through register \"CheminDeDonnees:inst\|74168:inst1\|49\" is 40.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "H source 22.700 ns + Longest register " "Info: + Longest clock path from clock \"H\" to source register is 22.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.900 ns) 2.900 ns H 1 CLK PIN_91 3 " "Info: 1: + IC(0.000 ns) + CELL(2.900 ns) = 2.900 ns; Loc. = PIN_91; Fanout = 3; CLK Node = 'H'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { H } "NODE_NAME" } } { "CHRONO.bdf" "" { Schematic "E:/SLEA/CHRONO.bdf" { { 24 64 232 40 "H" "" } { 280 320 360 296 "H" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.100 ns) + CELL(1.400 ns) 8.400 ns DiviseurDeFrequence:inst1\|7456:inst7\|5 2 REG LC1_H41 18 " "Info: 2: + IC(4.100 ns) + CELL(1.400 ns) = 8.400 ns; Loc. = LC1_H41; Fanout = 18; REG Node = 'DiviseurDeFrequence:inst1\|7456:inst7\|5'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.500 ns" { H DiviseurDeFrequence:inst1|7456:inst7|5 } "NODE_NAME" } } { "7456.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/7456.bdf" { { 328 344 408 408 "5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(1.400 ns) 13.300 ns DiviseurDeFrequence:inst1\|inst10 3 REG LC1_H27 18 " "Info: 3: + IC(3.500 ns) + CELL(1.400 ns) = 13.300 ns; Loc. = LC1_H27; Fanout = 18; REG Node = 'DiviseurDeFrequence:inst1\|inst10'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.900 ns" { DiviseurDeFrequence:inst1|7456:inst7|5 DiviseurDeFrequence:inst1|inst10 } "NODE_NAME" } } { "DiviseurDeFrequence.bdf" "" { Schematic "E:/SLEA/DiviseurDeFrequence.bdf" { { 312 1216 1280 392 "inst10" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(9.400 ns) + CELL(0.000 ns) 22.700 ns CheminDeDonnees:inst\|74168:inst1\|49 4 REG LC1_H33 11 " "Info: 4: + IC(9.400 ns) + CELL(0.000 ns) = 22.700 ns; Loc. = LC1_H33; Fanout = 11; REG Node = 'CheminDeDonnees:inst\|74168:inst1\|49'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.400 ns" { DiviseurDeFrequence:inst1|inst10 CheminDeDonnees:inst|74168:inst1|49 } "NODE_NAME" } } { "74168.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/74168.bdf" { { 680 1264 1328 760 "49" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.700 ns ( 25.11 % ) " "Info: Total cell delay = 5.700 ns ( 25.11 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "17.000 ns ( 74.89 % ) " "Info: Total interconnect delay = 17.000 ns ( 74.89 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "22.700 ns" { H DiviseurDeFrequence:inst1|7456:inst7|5 DiviseurDeFrequence:inst1|inst10 CheminDeDonnees:inst|74168:inst1|49 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "22.700 ns" { H {} H~out {} DiviseurDeFrequence:inst1|7456:inst7|5 {} DiviseurDeFrequence:inst1|inst10 {} CheminDeDonnees:inst|74168:inst1|49 {} } { 0.000ns 0.000ns 4.100ns 3.500ns 9.400ns } { 0.000ns 2.900ns 1.400ns 1.400ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "1.400 ns + " "Info: + Micro clock to output delay of source is 1.400 ns" { } { { "74168.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/74168.bdf" { { 680 1264 1328 760 "49" "" } } } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "16.700 ns + Longest register pin " "Info: + Longest register to pin delay is 16.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns CheminDeDonnees:inst\|74168:inst1\|49 1 REG LC1_H33 11 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_H33; Fanout = 11; REG Node = 'CheminDeDonnees:inst\|74168:inst1\|49'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { CheminDeDonnees:inst|74168:inst1|49 } "NODE_NAME" } } { "74168.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/74168.bdf" { { 680 1264 1328 760 "49" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.400 ns) + CELL(2.700 ns) 6.100 ns CheminDeDonnees:inst\|7446:inst4\|97~0 2 COMB LC8_H35 1 " "Info: 2: + IC(3.400 ns) + CELL(2.700 ns) = 6.100 ns; Loc. = LC8_H35; Fanout = 1; COMB Node = 'CheminDeDonnees:inst\|7446:inst4\|97~0'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "6.100 ns" { CheminDeDonnees:inst|74168:inst1|49 CheminDeDonnees:inst|7446:inst4|97~0 } "NODE_NAME" } } { "7446.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/7446.bdf" { { 264 680 744 304 "97" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.600 ns) + CELL(5.000 ns) 16.700 ns b1 3 PIN PIN_18 0 " "Info: 3: + IC(5.600 ns) + CELL(5.000 ns) = 16.700 ns; Loc. = PIN_18; Fanout = 0; PIN Node = 'b1'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "10.600 ns" { CheminDeDonnees:inst|7446:inst4|97~0 b1 } "NODE_NAME" } } { "CHRONO.bdf" "" { Schematic "E:/SLEA/CHRONO.bdf" { { 144 920 1096 160 "b1" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "7.700 ns ( 46.11 % ) " "Info: Total cell delay = 7.700 ns ( 46.11 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "9.000 ns ( 53.89 % ) " "Info: Total interconnect delay = 9.000 ns ( 53.89 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "16.700 ns" { CheminDeDonnees:inst|74168:inst1|49 CheminDeDonnees:inst|7446:inst4|97~0 b1 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "16.700 ns" { CheminDeDonnees:inst|74168:inst1|49 {} CheminDeDonnees:inst|7446:inst4|97~0 {} b1 {} } { 0.000ns 3.400ns 5.600ns } { 0.000ns 2.700ns 5.000ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "22.700 ns" { H DiviseurDeFrequence:inst1|7456:inst7|5 DiviseurDeFrequence:inst1|inst10 CheminDeDonnees:inst|74168:inst1|49 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "22.700 ns" { H {} H~out {} DiviseurDeFrequence:inst1|7456:inst7|5 {} DiviseurDeFrequence:inst1|inst10 {} CheminDeDonnees:inst|74168:inst1|49 {} } { 0.000ns 0.000ns 4.100ns 3.500ns 9.400ns } { 0.000ns 2.900ns 1.400ns 1.400ns 0.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "16.700 ns" { CheminDeDonnees:inst|74168:inst1|49 CheminDeDonnees:inst|7446:inst4|97~0 b1 } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "16.700 ns" { CheminDeDonnees:inst|74168:inst1|49 {} CheminDeDonnees:inst|7446:inst4|97~0 {} b1 {} } { 0.000ns 3.400ns 5.600ns } { 0.000ns 2.700ns 5.000ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
{ "Info" "ITDB_TH_RESULT" "BoutonPoussoir2:inst15\|inst BP1 H 5.700 ns register " "Info: th for register \"BoutonPoussoir2:inst15\|inst\" (data pin = \"BP1\", clock pin = \"H\") is 5.700 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "H destination 22.700 ns + Longest register " "Info: + Longest clock path from clock \"H\" to destination register is 22.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.900 ns) 2.900 ns H 1 CLK PIN_91 3 " "Info: 1: + IC(0.000 ns) + CELL(2.900 ns) = 2.900 ns; Loc. = PIN_91; Fanout = 3; CLK Node = 'H'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { H } "NODE_NAME" } } { "CHRONO.bdf" "" { Schematic "E:/SLEA/CHRONO.bdf" { { 24 64 232 40 "H" "" } { 280 320 360 296 "H" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.100 ns) + CELL(1.400 ns) 8.400 ns DiviseurDeFrequence:inst1\|7456:inst7\|5 2 REG LC1_H41 18 " "Info: 2: + IC(4.100 ns) + CELL(1.400 ns) = 8.400 ns; Loc. = LC1_H41; Fanout = 18; REG Node = 'DiviseurDeFrequence:inst1\|7456:inst7\|5'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "5.500 ns" { H DiviseurDeFrequence:inst1|7456:inst7|5 } "NODE_NAME" } } { "7456.bdf" "" { Schematic "c:/altera/90sp2/quartus/libraries/others/maxplus2/7456.bdf" { { 328 344 408 408 "5" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.500 ns) + CELL(1.400 ns) 13.300 ns DiviseurDeFrequence:inst1\|inst10 3 REG LC1_H27 18 " "Info: 3: + IC(3.500 ns) + CELL(1.400 ns) = 13.300 ns; Loc. = LC1_H27; Fanout = 18; REG Node = 'DiviseurDeFrequence:inst1\|inst10'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "4.900 ns" { DiviseurDeFrequence:inst1|7456:inst7|5 DiviseurDeFrequence:inst1|inst10 } "NODE_NAME" } } { "DiviseurDeFrequence.bdf" "" { Schematic "E:/SLEA/DiviseurDeFrequence.bdf" { { 312 1216 1280 392 "inst10" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(9.400 ns) + CELL(0.000 ns) 22.700 ns BoutonPoussoir2:inst15\|inst 4 REG LC1_H39 9 " "Info: 4: + IC(9.400 ns) + CELL(0.000 ns) = 22.700 ns; Loc. = LC1_H39; Fanout = 9; REG Node = 'BoutonPoussoir2:inst15\|inst'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.400 ns" { DiviseurDeFrequence:inst1|inst10 BoutonPoussoir2:inst15|inst } "NODE_NAME" } } { "BoutonPoussoir2.bdf" "" { Schematic "E:/SLEA/BoutonPoussoir2.bdf" { { 344 912 976 424 "inst" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.700 ns ( 25.11 % ) " "Info: Total cell delay = 5.700 ns ( 25.11 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "17.000 ns ( 74.89 % ) " "Info: Total interconnect delay = 17.000 ns ( 74.89 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "22.700 ns" { H DiviseurDeFrequence:inst1|7456:inst7|5 DiviseurDeFrequence:inst1|inst10 BoutonPoussoir2:inst15|inst } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "22.700 ns" { H {} H~out {} DiviseurDeFrequence:inst1|7456:inst7|5 {} DiviseurDeFrequence:inst1|inst10 {} BoutonPoussoir2:inst15|inst {} } { 0.000ns 0.000ns 4.100ns 3.500ns 9.400ns } { 0.000ns 2.900ns 1.400ns 1.400ns 0.000ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "3.100 ns + " "Info: + Micro hold delay of destination is 3.100 ns" { } { { "BoutonPoussoir2.bdf" "" { Schematic "E:/SLEA/BoutonPoussoir2.bdf" { { 344 912 976 424 "inst" "" } } } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "20.100 ns - Shortest pin register " "Info: - Shortest pin to register delay is 20.100 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(10.300 ns) 10.300 ns BP1 1 PIN PIN_28 1 " "Info: 1: + IC(0.000 ns) + CELL(10.300 ns) = 10.300 ns; Loc. = PIN_28; Fanout = 1; PIN Node = 'BP1'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "" { BP1 } "NODE_NAME" } } { "CHRONO.bdf" "" { Schematic "E:/SLEA/CHRONO.bdf" { { 48 64 232 64 "BP1" "" } { 40 328 360 56 "BP1" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(8.100 ns) + CELL(1.700 ns) 20.100 ns BoutonPoussoir2:inst15\|inst 2 REG LC1_H39 9 " "Info: 2: + IC(8.100 ns) + CELL(1.700 ns) = 20.100 ns; Loc. = LC1_H39; Fanout = 9; REG Node = 'BoutonPoussoir2:inst15\|inst'" { } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "9.800 ns" { BP1 BoutonPoussoir2:inst15|inst } "NODE_NAME" } } { "BoutonPoussoir2.bdf" "" { Schematic "E:/SLEA/BoutonPoussoir2.bdf" { { 344 912 976 424 "inst" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "12.000 ns ( 59.70 % ) " "Info: Total cell delay = 12.000 ns ( 59.70 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "8.100 ns ( 40.30 % ) " "Info: Total interconnect delay = 8.100 ns ( 40.30 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "20.100 ns" { BP1 BoutonPoussoir2:inst15|inst } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "20.100 ns" { BP1 {} BP1~out {} BoutonPoussoir2:inst15|inst {} } { 0.000ns 0.000ns 8.100ns } { 0.000ns 10.300ns 1.700ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "22.700 ns" { H DiviseurDeFrequence:inst1|7456:inst7|5 DiviseurDeFrequence:inst1|inst10 BoutonPoussoir2:inst15|inst } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "22.700 ns" { H {} H~out {} DiviseurDeFrequence:inst1|7456:inst7|5 {} DiviseurDeFrequence:inst1|inst10 {} BoutonPoussoir2:inst15|inst {} } { 0.000ns 0.000ns 4.100ns 3.500ns 9.400ns } { 0.000ns 2.900ns 1.400ns 1.400ns 0.000ns } "" } } { "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "c:/altera/90sp2/quartus/bin/TimingClosureFloorplan.fld" "" "20.100 ns" { BP1 BoutonPoussoir2:inst15|inst } "NODE_NAME" } } { "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "c:/altera/90sp2/quartus/bin/Technology_Viewer.qrui" "20.100 ns" { BP1 {} BP1~out {} BoutonPoussoir2:inst15|inst {} } { 0.000ns 0.000ns 8.100ns } { 0.000ns 10.300ns 1.700ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "156 " "Info: Peak virtual memory: 156 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Jan 24 17:20:54 2018 " "Info: Processing ended: Wed Jan 24 17:20:54 2018" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
Reference in a new issue View git blame Copy permalink