503 lines
91 KiB
Text
503 lines
91 KiB
Text
Classic Timing Analyzer report for Chronometre
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Wed Jan 24 17:22:10 2018
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Quartus II Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
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---------------------
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; Table of Contents ;
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---------------------
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1. Legal Notice
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2. Timing Analyzer Summary
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3. Timing Analyzer Settings
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4. Clock Settings Summary
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5. Parallel Compilation
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6. Clock Setup: 'H'
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7. tsu
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8. tco
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9. th
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10. Timing Analyzer Messages
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----------------
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; Legal Notice ;
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----------------
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Copyright (C) 1991-2009 Altera Corporation
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Your use of Altera Corporation's design tools, logic functions
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and other software and tools, and its AMPP partner logic
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functions, and any output files from any of the foregoing
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(including device programming or simulation files), and any
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associated documentation or information are expressly subject
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to the terms and conditions of the Altera Program License
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Subscription Agreement, Altera MegaCore Function License
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Agreement, or other applicable license agreement, including,
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without limitation, that your use is for the sole purpose of
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programming logic devices manufactured by Altera and sold by
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Altera or its authorized distributors. Please refer to the
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applicable agreement for further details.
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+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Timing Analyzer Summary ;
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+------------------------------+-------+---------------+----------------------------------+-----------------------------------------------------+------------------------------------------------------+------------+----------+--------------+
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; Type ; Slack ; Required Time ; Actual Time ; From ; To ; From Clock ; To Clock ; Failed Paths ;
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+------------------------------+-------+---------------+----------------------------------+-----------------------------------------------------+------------------------------------------------------+------------+----------+--------------+
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; Worst-case tsu ; N/A ; None ; 0.100 ns ; BP2 ; BoutonPoussoir2:inst16|inst ; -- ; H ; 0 ;
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; Worst-case tco ; N/A ; None ; 40.800 ns ; CheminDeDonnees:inst|74168:inst1|49 ; a1 ; H ; -- ; 0 ;
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; Worst-case th ; N/A ; None ; 5.700 ns ; BP1 ; BoutonPoussoir2:inst15|inst ; -- ; H ; 0 ;
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; Clock Setup: 'H' ; N/A ; None ; 42.02 MHz ( period = 23.800 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; H ; H ; 0 ;
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; Total number of failed paths ; ; ; ; ; ; ; ; 0 ;
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+------------------------------+-------+---------------+----------------------------------+-----------------------------------------------------+------------------------------------------------------+------------+----------+--------------+
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+--------------------------------------------------------------------------------------------------------------------+
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; Timing Analyzer Settings ;
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+---------------------------------------------------------------------+--------------------+------+----+-------------+
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; Option ; Setting ; From ; To ; Entity Name ;
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+---------------------------------------------------------------------+--------------------+------+----+-------------+
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; Device Name ; EPF10K70RC240-4 ; ; ; ;
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; Timing Models ; Final ; ; ; ;
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; Default hold multicycle ; Same as Multicycle ; ; ; ;
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; Cut paths between unrelated clock domains ; On ; ; ; ;
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; Cut off read during write signal paths ; On ; ; ; ;
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; Cut off feedback from I/O pins ; On ; ; ; ;
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; Report Combined Fast/Slow Timing ; Off ; ; ; ;
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; Ignore Clock Settings ; Off ; ; ; ;
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; Analyze latches as synchronous elements ; On ; ; ; ;
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; Enable Recovery/Removal analysis ; Off ; ; ; ;
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; Enable Clock Latency ; Off ; ; ; ;
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; Use TimeQuest Timing Analyzer ; Off ; ; ; ;
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; Minimum Core Junction Temperature ; 0 ; ; ; ;
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; Maximum Core Junction Temperature ; 85 ; ; ; ;
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; Number of source nodes to report per destination node ; 10 ; ; ; ;
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; Number of destination nodes to report ; 10 ; ; ; ;
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; Number of paths to report ; 200 ; ; ; ;
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; Report Minimum Timing Checks ; Off ; ; ; ;
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; Use Fast Timing Models ; Off ; ; ; ;
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; Report IO Paths Separately ; Off ; ; ; ;
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; Perform Multicorner Analysis ; Off ; ; ; ;
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; Reports the worst-case path for each clock domain and analysis ; Off ; ; ; ;
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; Removes common clock path pessimism (CCPP) during slack computation ; Off ; ; ; ;
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; Output I/O Timing Endpoint ; Near End ; ; ; ;
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+---------------------------------------------------------------------+--------------------+------+----+-------------+
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+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Clock Settings Summary ;
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+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
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; Clock Node Name ; Clock Setting Name ; Type ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
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+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
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; H ; ; User Pin ; None ; 0.000 ns ; 0.000 ns ; -- ; N/A ; N/A ; N/A ; ;
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+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
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Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
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+-------------------------------------+
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; Parallel Compilation ;
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+----------------------------+--------+
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; Processors ; Number ;
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+----------------------------+--------+
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; Number detected on machine ; 2 ;
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; Maximum allowed ; 1 ;
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+----------------------------+--------+
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+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
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; Clock Setup: 'H' ;
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+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
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; Slack ; Actual fmax (period) ; From ; To ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
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+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
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; N/A ; 42.02 MHz ( period = 23.800 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; H ; H ; None ; None ; 19.700 ns ;
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; N/A ; 42.02 MHz ( period = 23.800 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; H ; H ; None ; None ; 19.700 ns ;
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; N/A ; 42.37 MHz ( period = 23.600 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; H ; H ; None ; None ; 19.600 ns ;
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; N/A ; 42.37 MHz ( period = 23.600 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; H ; H ; None ; None ; 19.600 ns ;
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; N/A ; 42.37 MHz ( period = 23.600 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; H ; H ; None ; None ; 19.600 ns ;
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; N/A ; 42.55 MHz ( period = 23.500 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; H ; H ; None ; None ; 19.400 ns ;
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; N/A ; 42.55 MHz ( period = 23.500 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; H ; H ; None ; None ; 19.400 ns ;
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; N/A ; 42.92 MHz ( period = 23.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; H ; H ; None ; None ; 19.300 ns ;
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; N/A ; 42.92 MHz ( period = 23.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; H ; H ; None ; None ; 19.300 ns ;
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; N/A ; 42.92 MHz ( period = 23.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; H ; H ; None ; None ; 19.300 ns ;
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; N/A ; 43.10 MHz ( period = 23.200 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; H ; H ; None ; None ; 19.100 ns ;
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; N/A ; 43.10 MHz ( period = 23.200 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; H ; H ; None ; None ; 19.100 ns ;
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; N/A ; 43.48 MHz ( period = 23.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; H ; H ; None ; None ; 19.000 ns ;
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; N/A ; 43.48 MHz ( period = 23.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; H ; H ; None ; None ; 19.000 ns ;
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; N/A ; 43.48 MHz ( period = 23.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; H ; H ; None ; None ; 19.000 ns ;
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; N/A ; 43.67 MHz ( period = 22.900 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; H ; H ; None ; None ; 18.800 ns ;
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; N/A ; 43.67 MHz ( period = 22.900 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; H ; H ; None ; None ; 18.800 ns ;
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; N/A ; 44.05 MHz ( period = 22.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; H ; H ; None ; None ; 18.700 ns ;
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; N/A ; 44.05 MHz ( period = 22.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; H ; H ; None ; None ; 18.700 ns ;
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; N/A ; 44.05 MHz ( period = 22.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; H ; H ; None ; None ; 18.700 ns ;
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; N/A ; 46.51 MHz ( period = 21.500 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; H ; H ; None ; None ; 17.400 ns ;
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; N/A ; 46.51 MHz ( period = 21.500 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; H ; H ; None ; None ; 17.400 ns ;
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; N/A ; 46.95 MHz ( period = 21.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; H ; H ; None ; None ; 17.300 ns ;
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; N/A ; 46.95 MHz ( period = 21.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; H ; H ; None ; None ; 17.300 ns ;
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; N/A ; 46.95 MHz ( period = 21.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; H ; H ; None ; None ; 17.300 ns ;
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; N/A ; 47.17 MHz ( period = 21.200 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; H ; H ; None ; None ; 17.100 ns ;
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; N/A ; 47.17 MHz ( period = 21.200 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; H ; H ; None ; None ; 17.100 ns ;
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; N/A ; 47.17 MHz ( period = 21.200 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; H ; H ; None ; None ; 17.200 ns ;
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; N/A ; 47.17 MHz ( period = 21.200 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; H ; H ; None ; None ; 17.200 ns ;
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; N/A ; 47.62 MHz ( period = 21.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; H ; H ; None ; None ; 17.000 ns ;
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; N/A ; 47.62 MHz ( period = 21.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; H ; H ; None ; None ; 17.000 ns ;
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; N/A ; 47.62 MHz ( period = 21.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; H ; H ; None ; None ; 17.000 ns ;
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; N/A ; 47.85 MHz ( period = 20.900 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; H ; H ; None ; None ; 16.800 ns ;
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; N/A ; 47.85 MHz ( period = 20.900 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; H ; H ; None ; None ; 16.800 ns ;
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; N/A ; 47.85 MHz ( period = 20.900 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; H ; H ; None ; None ; 16.900 ns ;
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; N/A ; 47.85 MHz ( period = 20.900 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; H ; H ; None ; None ; 16.900 ns ;
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; N/A ; 48.31 MHz ( period = 20.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; H ; H ; None ; None ; 16.700 ns ;
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; N/A ; 48.31 MHz ( period = 20.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; H ; H ; None ; None ; 16.700 ns ;
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; N/A ; 48.31 MHz ( period = 20.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; H ; H ; None ; None ; 16.700 ns ;
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; N/A ; 48.54 MHz ( period = 20.600 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; H ; H ; None ; None ; 16.500 ns ;
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; N/A ; 48.54 MHz ( period = 20.600 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; H ; H ; None ; None ; 16.500 ns ;
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; N/A ; 48.54 MHz ( period = 20.600 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; H ; H ; None ; None ; 16.600 ns ;
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; N/A ; 48.54 MHz ( period = 20.600 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; H ; H ; None ; None ; 16.600 ns ;
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; N/A ; 49.02 MHz ( period = 20.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; H ; H ; None ; None ; 16.400 ns ;
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; N/A ; 49.02 MHz ( period = 20.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; H ; H ; None ; None ; 16.400 ns ;
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; N/A ; 49.02 MHz ( period = 20.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; H ; H ; None ; None ; 16.400 ns ;
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; N/A ; 49.26 MHz ( period = 20.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; H ; H ; None ; None ; 16.200 ns ;
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; N/A ; 49.26 MHz ( period = 20.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; H ; H ; None ; None ; 16.200 ns ;
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; N/A ; 49.26 MHz ( period = 20.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; H ; H ; None ; None ; 16.300 ns ;
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; N/A ; 49.26 MHz ( period = 20.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; H ; H ; None ; None ; 16.300 ns ;
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; N/A ; 49.75 MHz ( period = 20.100 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; H ; H ; None ; None ; 16.100 ns ;
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; N/A ; 49.75 MHz ( period = 20.100 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; H ; H ; None ; None ; 16.100 ns ;
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; N/A ; 49.75 MHz ( period = 20.100 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; H ; H ; None ; None ; 16.100 ns ;
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; N/A ; 50.00 MHz ( period = 20.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; H ; H ; None ; None ; 15.900 ns ;
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; N/A ; 50.00 MHz ( period = 20.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; H ; H ; None ; None ; 15.900 ns ;
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; N/A ; 50.51 MHz ( period = 19.800 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; H ; H ; None ; None ; 15.800 ns ;
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; N/A ; 50.51 MHz ( period = 19.800 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; H ; H ; None ; None ; 15.800 ns ;
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; N/A ; 50.51 MHz ( period = 19.800 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; H ; H ; None ; None ; 15.800 ns ;
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; N/A ; 50.76 MHz ( period = 19.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; H ; H ; None ; None ; 15.600 ns ;
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; N/A ; 50.76 MHz ( period = 19.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; H ; H ; None ; None ; 15.600 ns ;
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; N/A ; 51.28 MHz ( period = 19.500 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; H ; H ; None ; None ; 15.500 ns ;
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; N/A ; 51.28 MHz ( period = 19.500 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; H ; H ; None ; None ; 15.500 ns ;
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; N/A ; 51.28 MHz ( period = 19.500 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; H ; H ; None ; None ; 15.500 ns ;
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; N/A ; 51.55 MHz ( period = 19.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; H ; H ; None ; None ; 15.300 ns ;
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; N/A ; 51.55 MHz ( period = 19.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; H ; H ; None ; None ; 15.300 ns ;
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; N/A ; 52.08 MHz ( period = 19.200 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; H ; H ; None ; None ; 15.200 ns ;
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; N/A ; 52.08 MHz ( period = 19.200 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; H ; H ; None ; None ; 15.200 ns ;
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; N/A ; 52.08 MHz ( period = 19.200 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; H ; H ; None ; None ; 15.200 ns ;
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; N/A ; 52.91 MHz ( period = 18.900 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; H ; H ; None ; None ; 14.900 ns ;
|
|
; N/A ; 52.91 MHz ( period = 18.900 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; H ; H ; None ; None ; 14.900 ns ;
|
|
; N/A ; 53.76 MHz ( period = 18.600 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; H ; H ; None ; None ; 14.600 ns ;
|
|
; N/A ; 53.76 MHz ( period = 18.600 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; H ; H ; None ; None ; 14.600 ns ;
|
|
; N/A ; 54.64 MHz ( period = 18.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|5 ; H ; H ; None ; None ; 14.300 ns ;
|
|
; N/A ; 54.64 MHz ( period = 18.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|6 ; H ; H ; None ; None ; 14.300 ns ;
|
|
; N/A ; 54.64 MHz ( period = 18.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|8 ; H ; H ; None ; None ; 14.300 ns ;
|
|
; N/A ; 54.64 MHz ( period = 18.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; H ; H ; None ; None ; 14.300 ns ;
|
|
; N/A ; 54.64 MHz ( period = 18.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; H ; H ; None ; None ; 14.300 ns ;
|
|
; N/A ; 54.64 MHz ( period = 18.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; H ; H ; None ; None ; 14.300 ns ;
|
|
; N/A ; 54.64 MHz ( period = 18.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; H ; H ; None ; None ; 14.300 ns ;
|
|
; N/A ; 54.64 MHz ( period = 18.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; H ; H ; None ; None ; 14.300 ns ;
|
|
; N/A ; 54.64 MHz ( period = 18.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; H ; H ; None ; None ; 14.300 ns ;
|
|
; N/A ; 54.95 MHz ( period = 18.200 ns ) ; sequenceur2:inst17|inst3 ; CheminDeDonnees:inst|74168:inst2|49 ; H ; H ; None ; None ; 14.200 ns ;
|
|
; N/A ; 54.95 MHz ( period = 18.200 ns ) ; CheminDeDonnees:inst|74168:inst1|3 ; CheminDeDonnees:inst|74168:inst2|49 ; H ; H ; None ; None ; 14.200 ns ;
|
|
; N/A ; 54.95 MHz ( period = 18.200 ns ) ; CheminDeDonnees:inst|74168:inst8|49 ; CheminDeDonnees:inst|74168:inst2|49 ; H ; H ; None ; None ; 14.200 ns ;
|
|
; N/A ; 54.95 MHz ( period = 18.200 ns ) ; sequenceur2:inst17|inst3 ; CheminDeDonnees:inst|74168:inst2|29 ; H ; H ; None ; None ; 14.200 ns ;
|
|
; N/A ; 54.95 MHz ( period = 18.200 ns ) ; CheminDeDonnees:inst|74168:inst1|3 ; CheminDeDonnees:inst|74168:inst2|29 ; H ; H ; None ; None ; 14.200 ns ;
|
|
; N/A ; 54.95 MHz ( period = 18.200 ns ) ; CheminDeDonnees:inst|74168:inst8|49 ; CheminDeDonnees:inst|74168:inst2|29 ; H ; H ; None ; None ; 14.200 ns ;
|
|
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; DiviseurDeFrequence:inst1|inst10 ; H ; H ; None ; None ; 14.000 ns ;
|
|
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|5 ; H ; H ; None ; None ; 14.000 ns ;
|
|
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|6 ; H ; H ; None ; None ; 14.000 ns ;
|
|
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|8 ; H ; H ; None ; None ; 14.000 ns ;
|
|
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; H ; H ; None ; None ; 14.000 ns ;
|
|
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; H ; H ; None ; None ; 14.000 ns ;
|
|
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; H ; H ; None ; None ; 14.000 ns ;
|
|
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; H ; H ; None ; None ; 14.000 ns ;
|
|
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; H ; H ; None ; None ; 14.000 ns ;
|
|
; N/A ; 55.56 MHz ( period = 18.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; H ; H ; None ; None ; 14.000 ns ;
|
|
; N/A ; 55.87 MHz ( period = 17.900 ns ) ; CheminDeDonnees:inst|74168:inst8|3 ; CheminDeDonnees:inst|74168:inst2|49 ; H ; H ; None ; None ; 13.900 ns ;
|
|
; N/A ; 55.87 MHz ( period = 17.900 ns ) ; CheminDeDonnees:inst|74168:inst8|3 ; CheminDeDonnees:inst|74168:inst2|29 ; H ; H ; None ; None ; 13.900 ns ;
|
|
; N/A ; 55.87 MHz ( period = 17.900 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; H ; H ; None ; None ; 13.900 ns ;
|
|
; N/A ; 55.87 MHz ( period = 17.900 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; H ; H ; None ; None ; 13.900 ns ;
|
|
; N/A ; 56.50 MHz ( period = 17.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; DiviseurDeFrequence:inst1|inst10 ; H ; H ; None ; None ; 13.700 ns ;
|
|
; N/A ; 56.50 MHz ( period = 17.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|5 ; H ; H ; None ; None ; 13.700 ns ;
|
|
; N/A ; 56.50 MHz ( period = 17.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|6 ; H ; H ; None ; None ; 13.700 ns ;
|
|
; N/A ; 56.50 MHz ( period = 17.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; H ; H ; None ; None ; 13.800 ns ;
|
|
; N/A ; 56.50 MHz ( period = 17.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|8 ; H ; H ; None ; None ; 13.700 ns ;
|
|
; N/A ; 56.50 MHz ( period = 17.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; H ; H ; None ; None ; 13.700 ns ;
|
|
; N/A ; 56.50 MHz ( period = 17.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; H ; H ; None ; None ; 13.800 ns ;
|
|
; N/A ; 56.50 MHz ( period = 17.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; H ; H ; None ; None ; 13.700 ns ;
|
|
; N/A ; 56.50 MHz ( period = 17.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; H ; H ; None ; None ; 13.800 ns ;
|
|
; N/A ; 56.50 MHz ( period = 17.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; H ; H ; None ; None ; 13.700 ns ;
|
|
; N/A ; 56.50 MHz ( period = 17.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; H ; H ; None ; None ; 13.700 ns ;
|
|
; N/A ; 56.50 MHz ( period = 17.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; H ; H ; None ; None ; 13.700 ns ;
|
|
; N/A ; 56.50 MHz ( period = 17.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; H ; H ; None ; None ; 13.700 ns ;
|
|
; N/A ; 56.82 MHz ( period = 17.600 ns ) ; BoutonPoussoir2:inst15|inst ; CheminDeDonnees:inst|74168:inst8|49 ; H ; H ; None ; None ; 13.600 ns ;
|
|
; N/A ; 56.82 MHz ( period = 17.600 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; H ; H ; None ; None ; 13.600 ns ;
|
|
; N/A ; 56.82 MHz ( period = 17.600 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; H ; H ; None ; None ; 13.600 ns ;
|
|
; N/A ; 57.47 MHz ( period = 17.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; DiviseurDeFrequence:inst1|inst10 ; H ; H ; None ; None ; 13.400 ns ;
|
|
; N/A ; 57.47 MHz ( period = 17.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|5 ; H ; H ; None ; None ; 13.400 ns ;
|
|
; N/A ; 57.47 MHz ( period = 17.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|6 ; H ; H ; None ; None ; 13.400 ns ;
|
|
; N/A ; 57.47 MHz ( period = 17.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; H ; H ; None ; None ; 13.500 ns ;
|
|
; N/A ; 57.47 MHz ( period = 17.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|8 ; H ; H ; None ; None ; 13.400 ns ;
|
|
; N/A ; 57.47 MHz ( period = 17.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; H ; H ; None ; None ; 13.400 ns ;
|
|
; N/A ; 57.47 MHz ( period = 17.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; H ; H ; None ; None ; 13.500 ns ;
|
|
; N/A ; 57.47 MHz ( period = 17.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; H ; H ; None ; None ; 13.400 ns ;
|
|
; N/A ; 57.47 MHz ( period = 17.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; H ; H ; None ; None ; 13.500 ns ;
|
|
; N/A ; 57.47 MHz ( period = 17.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; H ; H ; None ; None ; 13.400 ns ;
|
|
; N/A ; 57.47 MHz ( period = 17.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; H ; H ; None ; None ; 13.400 ns ;
|
|
; N/A ; 57.47 MHz ( period = 17.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; H ; H ; None ; None ; 13.400 ns ;
|
|
; N/A ; 57.47 MHz ( period = 17.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; H ; H ; None ; None ; 13.400 ns ;
|
|
; N/A ; 57.80 MHz ( period = 17.300 ns ) ; BoutonPoussoir2:inst15|inst5 ; CheminDeDonnees:inst|74168:inst8|49 ; H ; H ; None ; None ; 13.300 ns ;
|
|
; N/A ; 57.80 MHz ( period = 17.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; H ; H ; None ; None ; 13.300 ns ;
|
|
; N/A ; 57.80 MHz ( period = 17.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; H ; H ; None ; None ; 13.300 ns ;
|
|
; N/A ; 58.48 MHz ( period = 17.100 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; DiviseurDeFrequence:inst1|inst10 ; H ; H ; None ; None ; 13.100 ns ;
|
|
; N/A ; 58.48 MHz ( period = 17.100 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; H ; H ; None ; None ; 13.200 ns ;
|
|
; N/A ; 58.48 MHz ( period = 17.100 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; H ; H ; None ; None ; 13.200 ns ;
|
|
; N/A ; 58.48 MHz ( period = 17.100 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; H ; H ; None ; None ; 13.200 ns ;
|
|
; N/A ; 58.48 MHz ( period = 17.100 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; H ; H ; None ; None ; 13.100 ns ;
|
|
; N/A ; 58.48 MHz ( period = 17.100 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; H ; H ; None ; None ; 13.100 ns ;
|
|
; N/A ; 58.82 MHz ( period = 17.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|1 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2 ; H ; H ; None ; None ; 13.000 ns ;
|
|
; N/A ; 58.82 MHz ( period = 17.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|1 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|3 ; H ; H ; None ; None ; 13.000 ns ;
|
|
; N/A ; 59.52 MHz ( period = 16.800 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|1 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|7 ; H ; H ; None ; None ; 12.900 ns ;
|
|
; N/A ; 59.52 MHz ( period = 16.800 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|1 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; H ; H ; None ; None ; 12.900 ns ;
|
|
; N/A ; 59.52 MHz ( period = 16.800 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|1 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; H ; H ; None ; None ; 12.900 ns ;
|
|
; N/A ; 59.52 MHz ( period = 16.800 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; H ; H ; None ; None ; 12.800 ns ;
|
|
; N/A ; 59.52 MHz ( period = 16.800 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|5 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; H ; H ; None ; None ; 12.800 ns ;
|
|
; N/A ; 62.50 MHz ( period = 16.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|1 ; H ; H ; None ; None ; 11.900 ns ;
|
|
; N/A ; 62.50 MHz ( period = 16.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|4 ; H ; H ; None ; None ; 11.900 ns ;
|
|
; N/A ; 62.50 MHz ( period = 16.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|5 ; H ; H ; None ; None ; 12.000 ns ;
|
|
; N/A ; 62.50 MHz ( period = 16.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|6 ; H ; H ; None ; None ; 12.000 ns ;
|
|
; N/A ; 62.50 MHz ( period = 16.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|8 ; H ; H ; None ; None ; 12.000 ns ;
|
|
; N/A ; 62.50 MHz ( period = 16.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; H ; H ; None ; None ; 12.000 ns ;
|
|
; N/A ; 62.50 MHz ( period = 16.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; H ; H ; None ; None ; 12.000 ns ;
|
|
; N/A ; 62.50 MHz ( period = 16.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; H ; H ; None ; None ; 12.000 ns ;
|
|
; N/A ; 62.50 MHz ( period = 16.000 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; H ; H ; None ; None ; 12.000 ns ;
|
|
; N/A ; 62.89 MHz ( period = 15.900 ns ) ; CheminDeDonnees:inst|74168:inst1|49 ; CheminDeDonnees:inst|74168:inst2|49 ; H ; H ; None ; None ; 11.900 ns ;
|
|
; N/A ; 62.89 MHz ( period = 15.900 ns ) ; CheminDeDonnees:inst|74168:inst1|49 ; CheminDeDonnees:inst|74168:inst2|29 ; H ; H ; None ; None ; 11.900 ns ;
|
|
; N/A ; 63.69 MHz ( period = 15.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|4 ; DiviseurDeFrequence:inst1|inst10 ; H ; H ; None ; None ; 11.700 ns ;
|
|
; N/A ; 63.69 MHz ( period = 15.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|1 ; H ; H ; None ; None ; 11.600 ns ;
|
|
; N/A ; 63.69 MHz ( period = 15.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|4 ; H ; H ; None ; None ; 11.600 ns ;
|
|
; N/A ; 63.69 MHz ( period = 15.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|5 ; H ; H ; None ; None ; 11.700 ns ;
|
|
; N/A ; 63.69 MHz ( period = 15.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|6 ; H ; H ; None ; None ; 11.700 ns ;
|
|
; N/A ; 63.69 MHz ( period = 15.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|8 ; H ; H ; None ; None ; 11.700 ns ;
|
|
; N/A ; 63.69 MHz ( period = 15.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; H ; H ; None ; None ; 11.700 ns ;
|
|
; N/A ; 63.69 MHz ( period = 15.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; H ; H ; None ; None ; 11.700 ns ;
|
|
; N/A ; 63.69 MHz ( period = 15.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; H ; H ; None ; None ; 11.700 ns ;
|
|
; N/A ; 63.69 MHz ( period = 15.700 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; H ; H ; None ; None ; 11.700 ns ;
|
|
; N/A ; 64.10 MHz ( period = 15.600 ns ) ; BoutonPoussoir2:inst15|inst ; CheminDeDonnees:inst|74168:inst2|49 ; H ; H ; None ; None ; 11.600 ns ;
|
|
; N/A ; 64.10 MHz ( period = 15.600 ns ) ; BoutonPoussoir2:inst15|inst ; CheminDeDonnees:inst|74168:inst2|29 ; H ; H ; None ; None ; 11.600 ns ;
|
|
; N/A ; 64.52 MHz ( period = 15.500 ns ) ; sequenceur2:inst17|inst3 ; CheminDeDonnees:inst|74168:inst2|15 ; H ; H ; None ; None ; 11.500 ns ;
|
|
; N/A ; 64.52 MHz ( period = 15.500 ns ) ; CheminDeDonnees:inst|74168:inst1|3 ; CheminDeDonnees:inst|74168:inst2|15 ; H ; H ; None ; None ; 11.500 ns ;
|
|
; N/A ; 64.52 MHz ( period = 15.500 ns ) ; CheminDeDonnees:inst|74168:inst8|49 ; CheminDeDonnees:inst|74168:inst2|15 ; H ; H ; None ; None ; 11.500 ns ;
|
|
; N/A ; 64.94 MHz ( period = 15.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; DiviseurDeFrequence:inst1|inst10 ; H ; H ; None ; None ; 11.400 ns ;
|
|
; N/A ; 64.94 MHz ( period = 15.400 ns ) ; sequenceur2:inst17|inst3 ; CheminDeDonnees:inst|74168:inst1|49 ; H ; H ; None ; None ; 11.400 ns ;
|
|
; N/A ; 64.94 MHz ( period = 15.400 ns ) ; CheminDeDonnees:inst|74168:inst1|3 ; CheminDeDonnees:inst|74168:inst1|49 ; H ; H ; None ; None ; 11.400 ns ;
|
|
; N/A ; 64.94 MHz ( period = 15.400 ns ) ; CheminDeDonnees:inst|74168:inst8|49 ; CheminDeDonnees:inst|74168:inst1|49 ; H ; H ; None ; None ; 11.400 ns ;
|
|
; N/A ; 64.94 MHz ( period = 15.400 ns ) ; sequenceur2:inst17|inst3 ; CheminDeDonnees:inst|74168:inst1|29 ; H ; H ; None ; None ; 11.400 ns ;
|
|
; N/A ; 64.94 MHz ( period = 15.400 ns ) ; CheminDeDonnees:inst|74168:inst1|3 ; CheminDeDonnees:inst|74168:inst1|29 ; H ; H ; None ; None ; 11.400 ns ;
|
|
; N/A ; 64.94 MHz ( period = 15.400 ns ) ; CheminDeDonnees:inst|74168:inst8|49 ; CheminDeDonnees:inst|74168:inst1|29 ; H ; H ; None ; None ; 11.400 ns ;
|
|
; N/A ; 64.94 MHz ( period = 15.400 ns ) ; BoutonPoussoir2:inst15|inst ; CheminDeDonnees:inst|74168:inst8|29 ; H ; H ; None ; None ; 11.400 ns ;
|
|
; N/A ; 64.94 MHz ( period = 15.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|1 ; H ; H ; None ; None ; 11.300 ns ;
|
|
; N/A ; 64.94 MHz ( period = 15.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|4 ; H ; H ; None ; None ; 11.300 ns ;
|
|
; N/A ; 64.94 MHz ( period = 15.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|5 ; H ; H ; None ; None ; 11.400 ns ;
|
|
; N/A ; 64.94 MHz ( period = 15.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|6 ; H ; H ; None ; None ; 11.400 ns ;
|
|
; N/A ; 64.94 MHz ( period = 15.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|8 ; H ; H ; None ; None ; 11.400 ns ;
|
|
; N/A ; 64.94 MHz ( period = 15.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; H ; H ; None ; None ; 11.400 ns ;
|
|
; N/A ; 64.94 MHz ( period = 15.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; H ; H ; None ; None ; 11.400 ns ;
|
|
; N/A ; 64.94 MHz ( period = 15.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; H ; H ; None ; None ; 11.400 ns ;
|
|
; N/A ; 64.94 MHz ( period = 15.400 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|2 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8 ; H ; H ; None ; None ; 11.400 ns ;
|
|
; N/A ; 65.36 MHz ( period = 15.300 ns ) ; BoutonPoussoir2:inst15|inst5 ; CheminDeDonnees:inst|74168:inst2|49 ; H ; H ; None ; None ; 11.300 ns ;
|
|
; N/A ; 65.36 MHz ( period = 15.300 ns ) ; BoutonPoussoir2:inst15|inst5 ; CheminDeDonnees:inst|74168:inst2|29 ; H ; H ; None ; None ; 11.300 ns ;
|
|
; N/A ; 65.36 MHz ( period = 15.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|6 ; H ; H ; None ; None ; 11.400 ns ;
|
|
; N/A ; 65.36 MHz ( period = 15.300 ns ) ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|4 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|7 ; H ; H ; None ; None ; 11.400 ns ;
|
|
; N/A ; 65.79 MHz ( period = 15.200 ns ) ; CheminDeDonnees:inst|74168:inst8|3 ; CheminDeDonnees:inst|74168:inst2|15 ; H ; H ; None ; None ; 11.200 ns ;
|
|
; N/A ; 66.23 MHz ( period = 15.100 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|5 ; H ; H ; None ; None ; 11.100 ns ;
|
|
; N/A ; 66.23 MHz ( period = 15.100 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|6 ; H ; H ; None ; None ; 11.100 ns ;
|
|
; N/A ; 66.23 MHz ( period = 15.100 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|8 ; H ; H ; None ; None ; 11.100 ns ;
|
|
; N/A ; 66.23 MHz ( period = 15.100 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; H ; H ; None ; None ; 11.100 ns ;
|
|
; N/A ; 66.23 MHz ( period = 15.100 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|3 ; H ; H ; None ; None ; 11.100 ns ;
|
|
; N/A ; 66.23 MHz ( period = 15.100 ns ) ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|1 ; DiviseurDeFrequence:inst1|8count:inst|f8count:sub|5 ; H ; H ; None ; None ; 11.100 ns ;
|
|
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ;
|
|
+-----------------------------------------+-----------------------------------------------------+------------------------------------------------------+------------------------------------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
|
|
|
|
|
|
+-----------------------------------------------------------------------------------+
|
|
; tsu ;
|
|
+-------+--------------+------------+------+-----------------------------+----------+
|
|
; Slack ; Required tsu ; Actual tsu ; From ; To ; To Clock ;
|
|
+-------+--------------+------------+------+-----------------------------+----------+
|
|
; N/A ; None ; 0.100 ns ; BP2 ; BoutonPoussoir2:inst16|inst ; H ;
|
|
; N/A ; None ; 0.000 ns ; BP1 ; BoutonPoussoir2:inst15|inst ; H ;
|
|
+-------+--------------+------------+------+-----------------------------+----------+
|
|
|
|
|
|
+-----------------------------------------------------------------------------------------------+
|
|
; tco ;
|
|
+-------+--------------+------------+-------------------------------------+--------+------------+
|
|
; Slack ; Required tco ; Actual tco ; From ; To ; From Clock ;
|
|
+-------+--------------+------------+-------------------------------------+--------+------------+
|
|
; N/A ; None ; 40.800 ns ; CheminDeDonnees:inst|74168:inst1|49 ; b1 ; H ;
|
|
; N/A ; None ; 40.800 ns ; CheminDeDonnees:inst|74168:inst1|49 ; a1 ; H ;
|
|
; N/A ; None ; 40.700 ns ; CheminDeDonnees:inst|74168:inst1|49 ; f1 ; H ;
|
|
; N/A ; None ; 40.700 ns ; CheminDeDonnees:inst|74168:inst1|49 ; c1 ; H ;
|
|
; N/A ; None ; 40.600 ns ; CheminDeDonnees:inst|74168:inst1|3 ; g1 ; H ;
|
|
; N/A ; None ; 40.500 ns ; CheminDeDonnees:inst|74168:inst2|29 ; G ; H ;
|
|
; N/A ; None ; 40.500 ns ; CheminDeDonnees:inst|74168:inst2|3 ; G ; H ;
|
|
; N/A ; None ; 40.500 ns ; CheminDeDonnees:inst|74168:inst2|29 ; E ; H ;
|
|
; N/A ; None ; 40.500 ns ; CheminDeDonnees:inst|74168:inst2|3 ; E ; H ;
|
|
; N/A ; None ; 40.500 ns ; CheminDeDonnees:inst|74168:inst2|29 ; D ; H ;
|
|
; N/A ; None ; 40.500 ns ; CheminDeDonnees:inst|74168:inst2|3 ; D ; H ;
|
|
; N/A ; None ; 40.500 ns ; CheminDeDonnees:inst|74168:inst2|49 ; C ; H ;
|
|
; N/A ; None ; 40.500 ns ; CheminDeDonnees:inst|74168:inst2|29 ; C ; H ;
|
|
; N/A ; None ; 40.500 ns ; CheminDeDonnees:inst|74168:inst2|49 ; B ; H ;
|
|
; N/A ; None ; 40.500 ns ; CheminDeDonnees:inst|74168:inst2|29 ; B ; H ;
|
|
; N/A ; None ; 40.500 ns ; CheminDeDonnees:inst|74168:inst2|49 ; A ; H ;
|
|
; N/A ; None ; 40.500 ns ; CheminDeDonnees:inst|74168:inst2|29 ; A ; H ;
|
|
; N/A ; None ; 40.300 ns ; CheminDeDonnees:inst|74168:inst1|3 ; d1 ; H ;
|
|
; N/A ; None ; 40.300 ns ; CheminDeDonnees:inst|74168:inst1|3 ; f1 ; H ;
|
|
; N/A ; None ; 40.300 ns ; CheminDeDonnees:inst|74168:inst1|3 ; e1 ; H ;
|
|
; N/A ; None ; 40.300 ns ; CheminDeDonnees:inst|74168:inst1|29 ; b1 ; H ;
|
|
; N/A ; None ; 40.300 ns ; CheminDeDonnees:inst|74168:inst1|29 ; a1 ; H ;
|
|
; N/A ; None ; 40.300 ns ; CheminDeDonnees:inst|74168:inst2|15 ; F ; H ;
|
|
; N/A ; None ; 40.200 ns ; CheminDeDonnees:inst|74168:inst1|29 ; d1 ; H ;
|
|
; N/A ; None ; 40.200 ns ; CheminDeDonnees:inst|74168:inst1|49 ; g1 ; H ;
|
|
; N/A ; None ; 40.200 ns ; CheminDeDonnees:inst|74168:inst1|29 ; g1 ; H ;
|
|
; N/A ; None ; 40.200 ns ; CheminDeDonnees:inst|74168:inst1|15 ; g1 ; H ;
|
|
; N/A ; None ; 40.200 ns ; CheminDeDonnees:inst|74168:inst1|29 ; e1 ; H ;
|
|
; N/A ; None ; 40.200 ns ; CheminDeDonnees:inst|74168:inst1|29 ; c1 ; H ;
|
|
; N/A ; None ; 40.200 ns ; CheminDeDonnees:inst|74168:inst2|49 ; G ; H ;
|
|
; N/A ; None ; 40.200 ns ; CheminDeDonnees:inst|74168:inst2|15 ; G ; H ;
|
|
; N/A ; None ; 40.200 ns ; CheminDeDonnees:inst|74168:inst2|3 ; C ; H ;
|
|
; N/A ; None ; 40.200 ns ; CheminDeDonnees:inst|74168:inst2|3 ; B ; H ;
|
|
; N/A ; None ; 40.200 ns ; CheminDeDonnees:inst|74168:inst2|3 ; A ; H ;
|
|
; N/A ; None ; 40.100 ns ; CheminDeDonnees:inst|74168:inst1|3 ; b1 ; H ;
|
|
; N/A ; None ; 40.100 ns ; CheminDeDonnees:inst|74168:inst1|3 ; a1 ; H ;
|
|
; N/A ; None ; 40.000 ns ; CheminDeDonnees:inst|74168:inst1|3 ; c1 ; H ;
|
|
; N/A ; None ; 39.900 ns ; CheminDeDonnees:inst|74168:inst1|29 ; f1 ; H ;
|
|
; N/A ; None ; 39.100 ns ; BoutonPoussoir2:inst15|inst ; BP1out ; H ;
|
|
; N/A ; None ; 38.800 ns ; BoutonPoussoir2:inst15|inst5 ; BP1out ; H ;
|
|
; N/A ; None ; 38.000 ns ; CheminDeDonnees:inst|74168:inst2|15 ; C ; H ;
|
|
; N/A ; None ; 38.000 ns ; CheminDeDonnees:inst|74168:inst2|15 ; B ; H ;
|
|
; N/A ; None ; 38.000 ns ; CheminDeDonnees:inst|74168:inst2|15 ; A ; H ;
|
|
; N/A ; None ; 37.900 ns ; CheminDeDonnees:inst|74168:inst1|15 ; b1 ; H ;
|
|
; N/A ; None ; 37.900 ns ; CheminDeDonnees:inst|74168:inst1|15 ; a1 ; H ;
|
|
; N/A ; None ; 37.900 ns ; CheminDeDonnees:inst|74168:inst2|49 ; F ; H ;
|
|
; N/A ; None ; 37.900 ns ; CheminDeDonnees:inst|74168:inst2|3 ; F ; H ;
|
|
; N/A ; None ; 37.800 ns ; CheminDeDonnees:inst|74168:inst1|15 ; f1 ; H ;
|
|
; N/A ; None ; 37.800 ns ; CheminDeDonnees:inst|74168:inst1|15 ; c1 ; H ;
|
|
; N/A ; None ; 37.700 ns ; CheminDeDonnees:inst|74168:inst2|15 ; E ; H ;
|
|
; N/A ; None ; 37.700 ns ; CheminDeDonnees:inst|74168:inst2|15 ; D ; H ;
|
|
; N/A ; None ; 37.600 ns ; CheminDeDonnees:inst|74168:inst2|29 ; F ; H ;
|
|
; N/A ; None ; 37.500 ns ; CheminDeDonnees:inst|74168:inst1|15 ; d1 ; H ;
|
|
; N/A ; None ; 37.500 ns ; CheminDeDonnees:inst|74168:inst1|15 ; e1 ; H ;
|
|
; N/A ; None ; 36.100 ns ; BoutonPoussoir2:inst15|inst ; Reset ; H ;
|
|
; N/A ; None ; 35.800 ns ; BoutonPoussoir2:inst15|inst5 ; Reset ; H ;
|
|
; N/A ; None ; 31.900 ns ; sequenceur2:inst17|inst3 ; Count ; H ;
|
|
+-------+--------------+------------+-------------------------------------+--------+------------+
|
|
|
|
|
|
+-----------------------------------------------------------------------------------------+
|
|
; th ;
|
|
+---------------+-------------+-----------+------+-----------------------------+----------+
|
|
; Minimum Slack ; Required th ; Actual th ; From ; To ; To Clock ;
|
|
+---------------+-------------+-----------+------+-----------------------------+----------+
|
|
; N/A ; None ; 5.700 ns ; BP1 ; BoutonPoussoir2:inst15|inst ; H ;
|
|
; N/A ; None ; 5.600 ns ; BP2 ; BoutonPoussoir2:inst16|inst ; H ;
|
|
+---------------+-------------+-----------+------+-----------------------------+----------+
|
|
|
|
|
|
+--------------------------+
|
|
; Timing Analyzer Messages ;
|
|
+--------------------------+
|
|
Info: *******************************************************************
|
|
Info: Running Quartus II Classic Timing Analyzer
|
|
Info: Version 9.0 Build 235 06/17/2009 Service Pack 2 SJ Web Edition
|
|
Info: Processing started: Wed Jan 24 17:22:09 2018
|
|
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Chronometre -c Chronometre
|
|
Info: Started post-fitting delay annotation
|
|
Info: Delay annotation completed successfully
|
|
Warning: Found pins functioning as undefined clocks and/or memory enables
|
|
Info: Assuming node "H" is an undefined clock
|
|
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
|
|
Info: Detected ripple clock "DiviseurDeFrequence:inst1|7456:inst7|5" as buffer
|
|
Info: Detected ripple clock "DiviseurDeFrequence:inst1|inst10" as buffer
|
|
Info: Clock "H" has Internal fmax of 42.02 MHz between source register "DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8" and destination register "DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2" (period= 23.8 ns)
|
|
Info: + Longest register to register delay is 19.700 ns
|
|
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5_H27; Fanout = 2; REG Node = 'DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8'
|
|
Info: 2: + IC(0.000 ns) + CELL(1.500 ns) = 1.500 ns; Loc. = LC5_H27; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1|8count:inst|f8count:sub|245'
|
|
Info: 3: + IC(0.000 ns) + CELL(0.300 ns) = 1.800 ns; Loc. = LC6_H27; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1|8count:inst|f8count:sub|246'
|
|
Info: 4: + IC(0.000 ns) + CELL(0.300 ns) = 2.100 ns; Loc. = LC7_H27; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1|8count:inst|f8count:sub|247'
|
|
Info: 5: + IC(0.000 ns) + CELL(0.300 ns) = 2.400 ns; Loc. = LC8_H27; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1|8count:inst|f8count:sub|248'
|
|
Info: 6: + IC(1.100 ns) + CELL(0.300 ns) = 3.800 ns; Loc. = LC1_H29; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1|8count:inst|f8count:sub|249'
|
|
Info: 7: + IC(0.000 ns) + CELL(0.300 ns) = 4.100 ns; Loc. = LC2_H29; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1|8count:inst|f8count:sub|250'
|
|
Info: 8: + IC(0.000 ns) + CELL(0.300 ns) = 4.400 ns; Loc. = LC3_H29; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1|8count:inst|f8count:sub|251'
|
|
Info: 9: + IC(0.000 ns) + CELL(0.300 ns) = 4.700 ns; Loc. = LC4_H29; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1|8count:inst|f8count:sub|302'
|
|
Info: 10: + IC(0.000 ns) + CELL(0.300 ns) = 5.000 ns; Loc. = LC5_H29; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|245'
|
|
Info: 11: + IC(0.000 ns) + CELL(0.300 ns) = 5.300 ns; Loc. = LC6_H29; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|246'
|
|
Info: 12: + IC(0.000 ns) + CELL(0.300 ns) = 5.600 ns; Loc. = LC7_H29; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|247'
|
|
Info: 13: + IC(0.000 ns) + CELL(0.300 ns) = 5.900 ns; Loc. = LC8_H29; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|248'
|
|
Info: 14: + IC(1.100 ns) + CELL(0.300 ns) = 7.300 ns; Loc. = LC1_H31; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|249'
|
|
Info: 15: + IC(0.000 ns) + CELL(0.300 ns) = 7.600 ns; Loc. = LC2_H31; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|250'
|
|
Info: 16: + IC(0.000 ns) + CELL(0.300 ns) = 7.900 ns; Loc. = LC3_H31; Fanout = 2; COMB Node = 'DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|251'
|
|
Info: 17: + IC(0.000 ns) + CELL(0.300 ns) = 8.200 ns; Loc. = LC4_H31; Fanout = 1; COMB Node = 'DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|302'
|
|
Info: 18: + IC(0.000 ns) + CELL(1.200 ns) = 9.400 ns; Loc. = LC5_H31; Fanout = 11; COMB Node = 'DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|302~5'
|
|
Info: 19: + IC(2.900 ns) + CELL(2.400 ns) = 14.700 ns; Loc. = LC3_H27; Fanout = 7; COMB Node = 'DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|302~5_wirecell'
|
|
Info: 20: + IC(3.000 ns) + CELL(2.000 ns) = 19.700 ns; Loc. = LC3_H31; Fanout = 2; REG Node = 'DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2'
|
|
Info: Total cell delay = 11.600 ns ( 58.88 % )
|
|
Info: Total interconnect delay = 8.100 ns ( 41.12 % )
|
|
Info: - Smallest clock skew is -0.100 ns
|
|
Info: + Shortest clock path from clock "H" to destination register is 11.800 ns
|
|
Info: 1: + IC(0.000 ns) + CELL(2.900 ns) = 2.900 ns; Loc. = PIN_91; Fanout = 3; CLK Node = 'H'
|
|
Info: 2: + IC(4.100 ns) + CELL(1.400 ns) = 8.400 ns; Loc. = LC1_H41; Fanout = 18; REG Node = 'DiviseurDeFrequence:inst1|7456:inst7|5'
|
|
Info: 3: + IC(3.400 ns) + CELL(0.000 ns) = 11.800 ns; Loc. = LC3_H31; Fanout = 2; REG Node = 'DiviseurDeFrequence:inst1|8count:inst4|f8count:sub|2'
|
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Info: Total cell delay = 4.300 ns ( 36.44 % )
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Info: Total interconnect delay = 7.500 ns ( 63.56 % )
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Info: - Longest clock path from clock "H" to source register is 11.900 ns
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Info: 1: + IC(0.000 ns) + CELL(2.900 ns) = 2.900 ns; Loc. = PIN_91; Fanout = 3; CLK Node = 'H'
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Info: 2: + IC(4.100 ns) + CELL(1.400 ns) = 8.400 ns; Loc. = LC1_H41; Fanout = 18; REG Node = 'DiviseurDeFrequence:inst1|7456:inst7|5'
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Info: 3: + IC(3.500 ns) + CELL(0.000 ns) = 11.900 ns; Loc. = LC5_H27; Fanout = 2; REG Node = 'DiviseurDeFrequence:inst1|8count:inst|f8count:sub|8'
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Info: Total cell delay = 4.300 ns ( 36.13 % )
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Info: Total interconnect delay = 7.600 ns ( 63.87 % )
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Info: + Micro clock to output delay of source is 1.400 ns
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Info: + Micro setup delay of destination is 2.600 ns
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Info: tsu for register "BoutonPoussoir2:inst16|inst" (data pin = "BP2", clock pin = "H") is 0.100 ns
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Info: + Longest pin to register delay is 20.200 ns
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Info: 1: + IC(0.000 ns) + CELL(10.300 ns) = 10.300 ns; Loc. = PIN_29; Fanout = 1; PIN Node = 'BP2'
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Info: 2: + IC(8.200 ns) + CELL(1.700 ns) = 20.200 ns; Loc. = LC1_H32; Fanout = 2; REG Node = 'BoutonPoussoir2:inst16|inst'
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Info: Total cell delay = 12.000 ns ( 59.41 % )
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Info: Total interconnect delay = 8.200 ns ( 40.59 % )
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Info: + Micro setup delay of destination is 2.600 ns
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Info: - Shortest clock path from clock "H" to destination register is 22.700 ns
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Info: 1: + IC(0.000 ns) + CELL(2.900 ns) = 2.900 ns; Loc. = PIN_91; Fanout = 3; CLK Node = 'H'
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Info: 2: + IC(4.100 ns) + CELL(1.400 ns) = 8.400 ns; Loc. = LC1_H41; Fanout = 18; REG Node = 'DiviseurDeFrequence:inst1|7456:inst7|5'
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Info: 3: + IC(3.500 ns) + CELL(1.400 ns) = 13.300 ns; Loc. = LC1_H27; Fanout = 18; REG Node = 'DiviseurDeFrequence:inst1|inst10'
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Info: 4: + IC(9.400 ns) + CELL(0.000 ns) = 22.700 ns; Loc. = LC1_H32; Fanout = 2; REG Node = 'BoutonPoussoir2:inst16|inst'
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Info: Total cell delay = 5.700 ns ( 25.11 % )
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Info: Total interconnect delay = 17.000 ns ( 74.89 % )
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Info: tco from clock "H" to destination pin "b1" through register "CheminDeDonnees:inst|74168:inst1|49" is 40.800 ns
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Info: + Longest clock path from clock "H" to source register is 22.700 ns
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Info: 1: + IC(0.000 ns) + CELL(2.900 ns) = 2.900 ns; Loc. = PIN_91; Fanout = 3; CLK Node = 'H'
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Info: 2: + IC(4.100 ns) + CELL(1.400 ns) = 8.400 ns; Loc. = LC1_H41; Fanout = 18; REG Node = 'DiviseurDeFrequence:inst1|7456:inst7|5'
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Info: 3: + IC(3.500 ns) + CELL(1.400 ns) = 13.300 ns; Loc. = LC1_H27; Fanout = 18; REG Node = 'DiviseurDeFrequence:inst1|inst10'
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Info: 4: + IC(9.400 ns) + CELL(0.000 ns) = 22.700 ns; Loc. = LC1_H33; Fanout = 11; REG Node = 'CheminDeDonnees:inst|74168:inst1|49'
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Info: Total cell delay = 5.700 ns ( 25.11 % )
|
|
Info: Total interconnect delay = 17.000 ns ( 74.89 % )
|
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Info: + Micro clock to output delay of source is 1.400 ns
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Info: + Longest register to pin delay is 16.700 ns
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Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC1_H33; Fanout = 11; REG Node = 'CheminDeDonnees:inst|74168:inst1|49'
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Info: 2: + IC(3.400 ns) + CELL(2.700 ns) = 6.100 ns; Loc. = LC8_H35; Fanout = 1; COMB Node = 'CheminDeDonnees:inst|7446:inst4|97~0'
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Info: 3: + IC(5.600 ns) + CELL(5.000 ns) = 16.700 ns; Loc. = PIN_18; Fanout = 0; PIN Node = 'b1'
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Info: Total cell delay = 7.700 ns ( 46.11 % )
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|
Info: Total interconnect delay = 9.000 ns ( 53.89 % )
|
|
Info: th for register "BoutonPoussoir2:inst15|inst" (data pin = "BP1", clock pin = "H") is 5.700 ns
|
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Info: + Longest clock path from clock "H" to destination register is 22.700 ns
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Info: 1: + IC(0.000 ns) + CELL(2.900 ns) = 2.900 ns; Loc. = PIN_91; Fanout = 3; CLK Node = 'H'
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Info: 2: + IC(4.100 ns) + CELL(1.400 ns) = 8.400 ns; Loc. = LC1_H41; Fanout = 18; REG Node = 'DiviseurDeFrequence:inst1|7456:inst7|5'
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Info: 3: + IC(3.500 ns) + CELL(1.400 ns) = 13.300 ns; Loc. = LC1_H27; Fanout = 18; REG Node = 'DiviseurDeFrequence:inst1|inst10'
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Info: 4: + IC(9.400 ns) + CELL(0.000 ns) = 22.700 ns; Loc. = LC1_H39; Fanout = 9; REG Node = 'BoutonPoussoir2:inst15|inst'
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|
Info: Total cell delay = 5.700 ns ( 25.11 % )
|
|
Info: Total interconnect delay = 17.000 ns ( 74.89 % )
|
|
Info: + Micro hold delay of destination is 3.100 ns
|
|
Info: - Shortest pin to register delay is 20.100 ns
|
|
Info: 1: + IC(0.000 ns) + CELL(10.300 ns) = 10.300 ns; Loc. = PIN_28; Fanout = 1; PIN Node = 'BP1'
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Info: 2: + IC(8.100 ns) + CELL(1.700 ns) = 20.100 ns; Loc. = LC1_H39; Fanout = 9; REG Node = 'BoutonPoussoir2:inst15|inst'
|
|
Info: Total cell delay = 12.000 ns ( 59.70 % )
|
|
Info: Total interconnect delay = 8.100 ns ( 40.30 % )
|
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Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
|
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Info: Peak virtual memory: 156 megabytes
|
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Info: Processing ended: Wed Jan 24 17:22:10 2018
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Info: Elapsed time: 00:00:01
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Info: Total CPU time (on all processors): 00:00:01
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